Simulating a s-par file created with ADS (advanced methodology)
Hello Community,This post is not about the straight forward methodology to simulate s-par file. Straight forward methodology : Create s-par file --> Use the nport component and select the s-par file...
View ArticleHow to simulate portion of the circuit with pre layout models & remaining...
In an LDO circuit for stability analysis, I want to simulate Error amplifier(opamp) alone schematic only and rest of the circuitry in dspf only. Since the circuit has both schematic & dspf , I am...
View ArticleNetlisting Unsuccessful for PEX Simulation in ADE/ADEXL
Hi All,I'm encountering an error while generating the netlist in ADE/ADEXL for post-layout simulation of my design. I have used the spectre output (PEX Output) as input of few block of my interest in...
View Articlename of nets inside deepprobe
Hi,I am using a DSPF file for the parasitic extraction and I want to use deepprobe at the top level to access voltages on nets deep inside the extracted netlist. I looks there is a disagreement between...
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VerilogA SR Latch with digital output
Hello, I am trying to create SR Latch with digital output with VerilogA.Below is my code.I wonder if someone can point me where I made mistake.I modified always statement with above or only always...
View ArticleInstallscape stops downloading
Installscape (newest version) seems to just stop downloading things. It doesn't error out, it doesn't report any issues. It just seems to stop. There's no error messages.Any suggestions? This is on...
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Re: command line to select psf directory to allow DC annotation on schematic
Hi,Does anyone know if it is possible to force an active ADE Explorer, via commands, to open a particular psf folder to allow DC voltage annotation or operating condition on the schematic?  I have an...
View ArticleAbout finding the cellname of .oa files
Hello,There's something wrong with our data, we only have sch.oa and layout.oa files left right now. How can I know the cellname of the corresponding sch.oa file? Another question is similar. How can I...
View ArticleHow to pause a Monte-Carlo simulation run and release license
Hi,I am running monte-carlo simulation, say 10 points in a run in ADE Assembler. Is it possible to pause one or a few of the running points and release the licenses? More importantly, is it possible to...
View ArticleAssert device check w/ pss.hb
Hello,The following assert statement is included in an .scs model file.vds_check_n1p8 assert subs=[nfet nfet_rf] expr="V(d,s)" min=-2 max=2In ADE Assembler I set Analog Sim Options > Check >...
View ArticleCan I pass value between runs in Transient Noise simulation?
I am doing transient noise simulation and would like to pass some values from the previous run to the next within one test.Basically, I need something like calcVal but for transient noise run.I am also...
View Articlewhy schematic and viva trace colors mismatched?
Often time a node on the schematic will not have a recognizable name attached, but clicking on a wire on the schematic in order to load it into VIva may highlight the wire in (say) dark blue.The trace...
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[SOLVED] [Verilog-A/AMS] Instantiating verilog-ams with analog input and...
EDIT: solution: Change reg OUT; into wire OUT;I instantiated verAMS_delay into verAMS_array_delay_v2.both modules pass extraction.Hierarchical editor recognizes the instantiated module but it shown in...
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[Verilog-A/AMS] Using a for loop to instantiate module
I need to generate multiple clocks with different delay.So, my plan is creating a single delay module and instantiate it using for loop which apply different delay then a single clock will drive all of...
View ArticleIs it possible to make the log window line wrap its text?
Is it possible to make the log window line wrap its text?The CIW does this but not simulation log window.
View ArticleSkill equivalent of "Open design in tab" in Assembler
Hi,In Assembler if I RMB one of the tests there is a menu option "Open design in tab"How I can open the test design in the tab using SKILL?Thank you.
View ArticleHow to assign two dimensional bus notation in schematics
This need just rises and I found out that it has been asked here.I have, let's say, 100 10-bit counters and would like to plot counter value as y-axis and counter ID as x-axis.From the link, this...
View ArticleSegmentation fault upon VerilogA compilation with an if condition
Hi,I am currently using ICADVM20.1-64b.500.24 and SPECTRE21.1.0.334.isr6 64bit. I already passed checksysconf for those and other cadence tools I currently have. My OS is CentOS 7. The server has 1TB...
View ArticleGrouping instances in layout
Hello,I have a basic issue, in the layout design I need to creat a group of some implemented devices, example I want to make the differential pair matched transistors as a one group after I have...
View ArticlePegasus LVS: how to enforce agreement of fins-per-finger parameter?
Hi! How can I make Pegasus to enforce checking the same number of fins per finger in both schematic and layout devices?Currently, this is being ignored in my setup. For example: a schematic device made...
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