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Segmentation fault upon VerilogA compilation with an if condition

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Hi,

I am currently using ICADVM20.1-64b.500.24 and SPECTRE21.1.0.334.isr6 64bit. I already passed checksysconf for those and other cadence tools I currently have. My OS is CentOS 7. The server has 1TB of RAM, 64 cores (128 threads), and plenty of storage space. I am already using "unlimit stacksize"

When I compile the simple attached verilogA file, it gives away a segmentation fault. This is during compilation and not even simulations.

community.cadence.com/.../new_5F00_res_5F00_estim.txt

When I change the condition to "freeze ==1" which is the opposite of what I want, it compiles successfully. When I change it "freeze!=1" it fails again.

Going back to an older version seems to fix the problem. For example, using ICADVM20.1 ISR21 and SPECTRE21.1 ISR1 compilation is successful.

I have been facing other "random segment faults" during simulations and I don't know if those things are somehow related.

Best regards.

Ahmed


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