Maestro open Design in Window instead of Tab
Hi,using RMB on a test and "Open Design in Tab" in Maestro obviously opens the schematic in a new tab and keeps the connection to this schematic, e.g. when annotating DC operating points it will show...
View Articleslide deck for "Getting the Best Spectre Simulator Results with Andrew Beckett"
Hi Andrew. Could the slide deck for your "Getting the Best Spectre Simulator Results with Andrew Beckett (Webinar)" get posted to the Cadence support sight? I just searched and wasn't able to find...
View ArticleImporting Synopsys .slib symbols to Cadence Virtuoso
Hi,I saw a post from a few years ago about importing '.slib/.sdb' (Synopsys' format) for symbols to Virtuoso. There were no ways to do that then. Just wanted to check if there have been any...
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Xcelium 1803 IE Card Config for Multi Power Supply
IE Card configuration only makes effect on hierarchy of level 1, if hierarchy level is over 2, IE Card configuration would behave unexpectedlyCASE1, there are 2 instances in TB, I0(cell1) and...
View ArticleWhen I was liberating a DFF cell that has three outputs {Q QN Q1},I get the...
The outputs {Q QN Q1},The QN and Q is a pair diff outputs . the liberate show me that there is no founction for this DFF cell;what should I do for this problem ! thanks for everyone
View ArticleImpedance matching between ports
Hello,I am simulating a balanced differential mixer and for the LO signal I am using an oscillator.I am having doubts about how to obtain the LO port impedance for this case? What is the best analysis...
View Articlecreating output expression while doing parametric sweep
Hi,I am running a parametric sweep in Cadence Virtuoso and I want to create an expression that takes the difference of a voltage for the last parameter value and the first parameter value. How can I do...
View ArticleAging Simulation Failure.(success in HCI mode, failure in PBTI mode and NBTI...
Has anyone ever done the Aging simulation?In my simulation results, the HCI mode changes in a normal way and reaches the degradation criteria of 0.1 in approximately 7 years.However, when simulating...
View ArticleSet Use No DM option to default when create library in library manager
I set "ddserv.lib dmchoice string 'No DM'" in .cdsenv file, but it didn't take effect.
View ArticleSetting supply sensitivity by default for any new pin in Virtuoso Schematic
Hi, I would like to set the supply sensitivity information of any new instantiated pin in Virtuoso Schematic Editor by default as "Both". The default that we have right now is "None". I would like to...
View Articlerun plan - pass a filepath though the calcVal() function
Hi all,within a run plan (ADE Assembler) I wanted to run a first transient TEST0, save the final nodes operation point (the writefinal inside the transient options) and then retrieve the saved file in...
View ArticleIssue with Level=3 MOS model in Spectre
Hi, I am trying to simulate the FET model that I downloaded from the manufacturer. I have always been able to use Spice models by using the statement:simulator lang=spicebefore the model. But this...
View ArticleSpectre error: parameter range violation
Hi all,I’m encountering error in Virtuoso ADE L during Spectre simulation for a BSIM-CMG device model:Error found by spectre during initial setup. ERROR: pmos: Model parameter NSD=1.00e+25 should not...
View ArticleThe spec of adexl
Hi，allIn ADE XL, what is the function of the "info" field in the Spec section under Outputs Setup?Additionally, how can I input a reference voltage V1 in the Spec such that it only appears as...
View Article2 tests sim with different temperature
Hi,friendsI have two tests, test1 and test2. Test1 needs to simulate only the 25°C value under the corner to obtain V1, while test2 must simulate three temperatures (-40°C, 25°C, and 125°C) under the...
View ArticleCross-hierarchy control of node voltage？
Hi,friendsI have an amplifier simulation circuit named TB, which contains an AMP module. The next hierarchy level of AMP includes modules like BG, OTA, and TRIM. Suppose the input of TRIM is DEC0. Is...
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PSS+PNoise with voltage source noise and device noise
Hi,I am using ADE Assembler in IC23.1 for my simulation.In my test bench, a "vpulse" is driving a clock booster. I would like to measure the Jee at clock booster output, including previous stage...
View ArticleSpectre out.cluttered with Start ADE session ID messages
IC23.1-64b.ISR14.32Hi,How can I stop the tool from cluttering my spectre.out with hundreds of lines like:Start ADE session ID: yooZQMVeJ0X3QiXStart ADE session ID: yooZQMVeJ0X3QiXStart ADE session ID:...
View ArticleCadence LVS Error in the Schematic vs Layout
Hi All,I am trying to perform LVS between a custom standard cell schematic and layout. I have the schematic, layout and the symbol views to this cell and when running the LVS, I run into the following...
View Article2D Sweep in Spectre Netlist
Hi, I want to know how to sweep 2 parameters at the same time in a Spectre netlist.For example, following is sweep W and L separately:// DC sweepdcSweepW dc param=WMASK start=9u stop=0.288u...
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View list and Stop list in Cadence PVS
Hi all!I want to know about what is "View List" and "Stop List" options in the PVS LVS run form Input->schematic, I tried looking this in pvsuser and pvsref docs, but could'nt get enough info to...
View Article"DrgEnb" of techDisplays class in Virtuoso Techfile IC5.1 & IC6.1
I have a question about DrgEnb in the techDisplays class. When I set DrgEnb to 't' and 'nil' in an arbitrary layer, dragging is possible in both cases. I'm curious why that is. Shouldn't dragging be...
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IC problem in simulation
hi,I'm trying to run transient simulation on my design. from some reason when simulation starts, all internal design terminals are starting from DC level 0(even pre-post inverter) and then spiking up...
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The tran+stb simulation phase curve declines from -150 degree
Hi all, I've encountered an unusual issue. When performing tran-STB co-simulation on an OPA with switched-capacitor feedback, I observed its phase curve starting to decline from -150°. As this is my...
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Different PSS and Pnoise result with different Fund and sample_ratio settings
Hello everyone,I am using ADE assembler in IC23.1 to simulation my circuit, which include a 25% dutycycle generator (working frequency is fck) followed with a div-4 (driven by 2 stage clock buffer).I...
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