Performing Monte-Carlo simulation with AMS
Hi,I am relatively new to working with AMS. However, I have a design with a digital block that if simulated with its schematic view with spectre, takes a week to finish. Substituting the digital with...
View ArticleBatch run simulations with different initial conditions.
I have a design. Now I want to simulate it in a loop, everytime changing its initial conditions and wiring a bit. I then want the frequency of the output signal to be stored in a tabular form in a...
View ArticleHow to get application type and/or window id from session
Hi,Is it possible to get an application type and window id from a session?I tried axlGetSessionWindowNumber(axlGetWindowSession()) but the returned window number different from one returned by...
View Articlemaestro Results pane order. How to reset back to default?
If I have inadvertently clicked the Output heading and all results have gone into alphabetical order how do you get the original order back that matches the Outputs Setup pane?IC6.1.8-64b.500.19
View ArticleThe way to define variable correlated to ac simulation in .scs model
Greetings,I would like to run AC sim in one test once in case of two sub-conditions1) ac source1 active with acm1 = 1, ac source2 off with acm2=02) ac source1 off with acm1 = 0, ac source2 active with...
View ArticleVerilog netlist wont explicit bit connected to bus pin
Hi, Im using verilog netlister (lunch--> plugins-->simuilation--> systemVerilog) to netlist my schematic. Now I have an instance with 32 bit pin input (input rstb<31:0>). In the...
View ArticleHow to create auto pin under the cursor select
While I use create pin by auto mode, the new generated pin always put on start or end of line. I want to let the pln location follow the cursor select. How can I achieve it? Thank you.
View Articleinnovus saveNetlist issue (UPF_IS_1)
When I saveNetlsit in my innovus , I found Some PG nets which connected to std cell PG pins have been renamed , from VDD to VDD_UPF_IS_1, in netlist it shows like:.VSS...
View ArticleNetlisting Unsuccessful for PEX Simulation in ADE/ADEXL
Hi All,I'm encountering an error while generating the netlist in ADE/ADEXL for post-layout simulation of my design. I have used the spectre output (PEX Output) as input of few block of my interest in...
View ArticlePcells LVS fail. Master not found
Hello,I have create some pcell which are only layout. When I use them in the design the DRC checks (assura) runs correctly. The LVS instead give an error:Reading the design data...ERROR (AVVSI-10001):...
View Articlenetlist creation issue
Hi,I try two ways to create netlists of my testbench (IC618, maestro, spectre):1. right click test name --> recreate the netlist --> the result is fine2. right click the sim result --> view...
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How to change Default Decend View type
I dont know why, the default decend view "schematic" should be prior to others, but now it changes to "schematic_behav", (Figure 1)And another strange problem is when I Check Hierachy, the...
View Articlehow to trim metal(overhangs over vias)
Hi, is there any skill to trim metals near vias, pins etc to remove overhangs
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Empty R reporting in Parasitic Backannotation
Hello, I was following Parasitic Aware Design Flow RAK and everything works well if I used the simulation results provided from the RAK.However I cannot have R reporting works if I simulate the circuit...
View Articleoutput setup shows a yellow row
Hi,When i edit the output setup in maestro/output setup, i got a yellow row and CIW reports: hiCreateListBoxField: Requested numRows does not fit in given field space. List resized to fit.What does...
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cdsterm info sometimes does not show?
I often have situations where some, but not all of my cdsterm node voltages don't show.For example, the following cell originally had lower case r and s inputs, the voltages showed when I enabled...
View ArticleVerilogA End of File
Hi, I am reading data from a file which contains the pixel values of column of image. I am performing the transient analysis using spectre to get the output (out here) at each time event. I have tried,...
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3-bit flash ADC design
i'm trying to simulate the 3-bit flash adc design but i keep getting" ERROR (USIMDB-11501): The UltraSim simulator encountered illegal voltage source and inductor loop in the instance (element or node)...
View Articleswitch layer when creating a path in 6.1.8?
I recall in older version of Virtuoso, when creating a path, the command menu (F3) had an option to switch to an adjacent layer and would plop a via down at the junction. In 6.1.8 this is missing from...
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SA Register output issue
Hello, I am implementing a 10-bit sar adc using cadence. I have been stuck in the SA Register part. I am using 22 numbers of D-Flipflops. The single flip-flop circuit is functioning absolutely fine and...
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