[SOLVED] [Verilog-A/AMS] Instantiating verilog-ams with analog input and digital output

EDIT: solution: Change reg OUT; into wire OUT;


I instantiated verAMS_delay into verAMS_array_delay_v2.
both modules pass extraction.
Hierarchical editor recognizes the instantiated module but it shown in red like in the picture below.
When I tried to simulate it, it has the error below.
Could someone point me where I made mistake?