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ahdlLib quantizer Block
Hello,I am using quantizer block from ahdlLib block. I am applying a sawtooth wave and then quantized it into 4 levels. Quantized output should be equally quantized in time and value. But somehow I am...
View ArticleMaestro Expression Migration Problem
Due to a project organization change some designs/testbenches were migrated to a new database/library name. I had four similar designs with similar testbenches that were migrated and then updated with...
View ArticleCan I tailor the transition from Assembler to Explorer, like using...
Hi,usually I work in Assembler, but often need e.g. to expand, re-arrange, rename, etc. a test. Too often I accidentially click to the blue arrow, and jump to Explorer. How can I prevent this? Need for...
View ArticleChanging Schematic Property Value in CIW Window
I had a way to change a schematic property value in the CIW window but I can't remember it.Example:A transistor device has the parameters of length and width. These devices are set up with a range of...
View ArticleLayoutXL creating auto connectivity of custom cell
Hi,I have question about auto generation the connectivity of my custom cell layout. When we update the instance from source, if it is from foundry device level, the tool will help to generate the...
View ArticleHow to get statistical corner by seed and run id in sigma-scaled sampling?
Hi,if I create after normal MC a statistical corner, I have two options, by seed/id or by saving all individual stat. variables. The latter is more stable for testbench changes, but the 1st is faster...
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Could I run only one "runPlan" in Verifier?
As the screenshot below, I have set 5 runPlans (RP_handroom, RP_stb, RP_noise...) in one implementation,this is becaulse I include many testbenches/configs in one maestro.When I clik "run", all 5...
View ArticleCDL netlist format
I have CDL net lists using different ways to connect the substrate pin of a transistor:Q1 net1 net2 net3 [net4] npn M=1Q2 net1 net2 net3 npn M=1 $SUB=net4Q3 net1 net2 net3 net4 npn M=1Q4 net1 net2 net3...
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Sweep the real inductor value in virtuoso
Greetings ,I have a question regarding real inductors. In virtuoso , can we sweep the real inductor value by script or by sweep itself or are we forced to vary the parameters of the inductor ? In other...
View Articleschematic vs symbol pinorder.
I am back doing design after a laborious period doing layout/tapeout, and am seeing a difference between how globals were treated before and how they are currently. I must be doing something different...
View ArticleWriting into a file in Verilog-A Model
Dear All,I want to write the data into a file in the Verilog-A model.I tried something like below. It is not showing any errors, but the file is still empty. By the way, reading from this file works...
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Can't get results from a PAC sim
Hi,I am trying to build up a dc-dc converter model, but I am having issues with PAC analysis. I put together a very simple modulator show below. I can get transient and PSS sims to work just fine. All...
View ArticleDocumentation about VNL netlist format
Hi there,Is there any documentation about VNL netlist format?I need to parse such netlists for debugging/statistics.Thank you,Marcel
View Articlehow to update "design" when copy testbench
Hi,I need to copy many test bench from old lib to the new lib. I wish the design of the testbench can be updated by default (to the view in the new lib). I have set option: update the instance, but...
View ArticlePlot all digital traces in one subwindow
Hi,I am simulating a mixed-signal design, and I have saved in the ADE digital signals obtained via the conversion function awvAnalog2Digital from ViVa. The first time I convert the signals from analog...
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Calculator error on arithmetic operation on the reading of digital bus
I have a digital bus as an output of verilog block.Then putting these expressions on calculator gives me error.value(VT("/COUNTER4V_A<31:0>") 1u ) / 9997EDIT :...
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How to stop Ocean script from UINX
Hello.I`m using IC6.1.8This simulation is just "sweepsAndCorners" and There are lots pointsI found the problem. so I try to stop script while script is workingHow to stop Ocean script from UINX?I ran...
View Articlehow to section comment in a DSPF file
Hi,I am using an extracted netlist DSPF file and I need to comment a bunch of lines. I was wondering if there is a possibility to comment everything at once. I tried /* */ but it doesn't work and...
View ArticleIs there a quicker way to display an output after sims?
I'm sure there is one, but in all the toolbars/assistants etc, I can't find a way after a sim to shorten:ADE_Explorer> Setup > Select on design > outputs to be plotted ------ then click on...
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Layout Cannot Show PDK Instance Graph
1. Configuration: Cadence IC617 + MMSIM151 + Calibre 2015.2. PDK: TSMC CRN65GP, install using pdkInstall.pl in PDK.3. I am studying the LNA tutorial given by TSMC docs. The schematic simulation is...
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