Quantcast
Channel: Cadence Custom IC Design Forum
Browsing all 4904 articles
Browse latest View live

Keysight ADS schematic into Virtuoso

Hi All, is there a way to bring in Keysight ADS schematic (originally created in Virtuoso and exported to ADS using the dynamic link option ) back into Virtuoso ?No major changes were done after...

View Article


Image may be NSFW.
Clik here to view.

How to check the load capacitance of a node in cadence virtuoso?

Hello everyone.How to check the load capacitance of a node in cadence virtuoso?For example,I want to get the total load capacitance of the "sample_convert" node in the image below. Is there any...

View Article


Image may be NSFW.
Clik here to view.

Running Spectre simulation and then plotting in ViVA by using system()...

Dear All; I need to run multiple spectre simulations from MATLAB (using system() command to fire transient simulations) as I need to modify the netlist for changing some parameters of the circuit in...

View Article

Image may be NSFW.
Clik here to view.

When I open the simulation state which I create before, I can not reload the...

View Article

Cadence understand Poly resistor as a poly contact problem

Hello,I am using Cadence Virtuoso tools version IC6.1.8-64b.500.6 with the Assura package.During the layout of the poly resistor, I usually insert it as a PCELL by using "Connectivity" >...

View Article


Create Label window disappears after selecting auto

Create Label window disappears after selecting "auto" option.I need to restart Cadence to bring this window back.Any suggestion for this?

View Article

probe a structure for all layout layers used in its build?

Is it possible to select a structure - in my case a fluid guard ring - and display every layer used in its  construction? 

View Article

Image may be NSFW.
Clik here to view.

Continuous & Discrete-Time behaviour of a Switched-Cap. Integrator circuit

Dear guys,I would have the following question at the end of this text.Since I have read that Andrew Beckett also seems to have extremely profound experiecne  here (e.g. topic...

View Article


stability analysis RC coupled Vs RC decoupled

Is there an issue with Virtuoso stb analysis and coupled C? I have a regulator giving a reasonable RCdecoupled phase margin but when RCcoupled is chosen then the PM drops below zero. If i use the...

View Article


Issue with importing csv file to the ADEXL outputs

Hi,I have transistors in the schematic named Mxx<5:0> and want to observe the "gm" of Mxx<5>. After accessing this in the results browser and storing in the outputs and then exporting it as...

View Article

LVS Port Mismatch Errors with CDL Netlist

Hello,I have a schematic and layout that I'm trying to run through LVS using PVS 16.15.The schematic contains a number of sub-blocks which come from an IP provider andonly have a CDL netlist available....

View Article

How can I use a paramset to define a dc simulation for certain parameter...

Hi,I need a pure spectre solution, and I expect either to require the dc analysis statement and the sweep command. I want to run a design for certain combinations of Iload and temp.However, all I tried...

View Article

Image may be NSFW.
Clik here to view.

parasitic exclusion not working in PAD

In this previous post link at the end of this mail , Andrew demonstrates in the Parasitic Aware Design tool, how the combination of R and C cell filers then individual net filters set to "none", net...

View Article


Can I generate layout from source but not from the same hierarchy level?

Let's say I have this hierarchy in the schematic:TOP|--I1|   |--M1, M2, I3||--I2    |--M1, M2, M3, I4So, I1 and I2 are on the same hierarchy level.I do not want to create the layout of I1 and I2.what I...

View Article

Virtuoso Schematic Bus Connection

Dear community, in a newer Virtuoso version (ICADVM20.1-64b.500.22) the bus system does not work as usual. For example I have a source with 3 instances V1<1:3> and I want to multiply each signal...

View Article


Passing LVS without making the well tap in the current hierarchy

In order to save area and other reasons related with the process technology, I need to not draw the well tap in the layout.I plan to add the well tap later in the higher hierarchy.Obviously, LVS...

View Article

Image may be NSFW.
Clik here to view.

How to use a CSV file in Cadence?

I am using cadence version - IC6.1.5.500.15I want to use a noisy signal as an input to my circuit in cadence, and I took the following steps:-Step 1:- I created a CSV format file of the noisy signal...

View Article


Image may be NSFW.
Clik here to view.

My download manager is no working with Cadence 17.4 installation

Hi Expert,I am from TI and first time to use Cadence. Yesterday I install Cadence 17.4 in TI download link. But I have two questions as below:1.  The download manager is not working. See below...

View Article

Monte-Carlo output for mean+-x*sigma?

Hi Experts,our customers requires us to report MC results in terms of 5-sigma limits, but this is not a direct output in Assembler. I would like to check these 5-sigma values vs the spec limits. Can I...

View Article

Wire Assistant in layout loosing connectivity

Hello,I am using Cadence Virtuoso version IC6.1.8-64b.500.6I am newly facing a problem with the Wire Assistant from the layout, my problem is that when I click on the connection from the schematic it...

View Article
Browsing all 4904 articles
Browse latest View live


<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>