Cadence understand Poly resistor as a poly contact problem

Hello,

I am using Cadence Virtuoso tools version IC6.1.8-64b.500.6 with the Assura package.

During the layout of the poly resistor, I usually insert it as a PCELL by using "Connectivity" > "Generate"> "Selected from Source". The resistor is then inserted with all required layers.

During verifying my circuit with CAS, it shows me shorts in the locations between the resistor terminals, it means he understands the poly as contact shortening the two terminals of what is supposed to be the resistor.

How can inform Cadence to treat it as a resistor?

However, during the LVS check, the design pass correctly

While I have many resistors in my design, it is becoming annoying to differentiate between real shorts and those shorts in my design.

Thank you

Regards