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Adding text note to the layout
Is there a way to do this just like we do in schematic?I found this solution but I cannot delete or move it once it is placed in the layout.
View ArticleIs it possible to modify the datasheet template (xml file)?
Is it possible to modify the datasheet template (xml file)? How?
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unwanted unknown layer in the layout
Some block show this unknown layer when instantiated.This layer is not there in the layout.The outer rectangle should not be there.any suggestion is appreciated.apologize if this turns out to be a very...
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MAESTRO CORNER SETUP
How can I define set corners not by multiply number of variables, but as "parallel" set.Not to run 25 corners , only 5 : 0 -0 , 1-1, 2-2, 3-3, 4-4, 8-8. This option was in old ADE in parameter analysis...
View Articleautomatic routing using specific metal layer
How can I tell cadence to do automatic routing using certain metal layer only, e.g., only metal2 and metal3 ?Which documentation should I consult to regarding this?I found some explanation about...
View ArticleHow to add dyn_floatdcpath into ADE
I found the following example of using dyn_floatdcpath. But I couldn't figure out how to set it in ADEÂ * Dynamic check.simulator lang=spectreglobal 0parameters vdc=1include "./mos_bsim4.scs"opt1...
View Articleglobal pins
I have many global pins(VDD! and VSS!). I f I connect them with metal, resistance increase. I want to connect global pins without physical in layout. Can I connect them in pex extraction and LVS.Â
View Articleslow pointer movement when creating pin automatically in the layout
Slow pointer movement when creating pin automatically in the layout.I am using IC6.1.8
View ArticleIssue with Import ADE-XL State to Cadence Explorer.
Hi There, I am using icfb 6.1.8. I am trying to import old ADE-XL setup to newly created Explorer. But, When I do session >> Import setup and try to look for ADE-Xl State through new pop-up...
View ArticleLayers visibility issue in hierarchical layout design
Hello,I am in the second hierarchical level of my layout design, I have inserted a layout block from the first hierarchical, I did it from "Connectivity"> "Generate" > "Selected from source". The...
View Articleis there something like "Net Highlighting" in the layout?
is there something like "Net Highlighting" in the layout?The closest thing I can find is Display Controls --> Nets.
View ArticleImporting Digital Standard Cells from PDK data
Hello everybody,I have some problems including the digital library with the standard cells in it in Virtuoso (same accounts for the standard IO-library).I have included the cds.lib files from this PDK...
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converting an analog signal into digital and saving the formula on the ADE...
Hi all,I am doing a DC simulation and I desire to display the value of an analog signal as 0 or 1 depending on whether the voltage level is 0 or 1.8V.In a second step I'll need to do that also for a...
View ArticleClear/close a 'running' ADE-XL
A situation I run into often is the need to close and clear an ADE-XL session, primarily to get a fresh starting point without closing my Cadence session.The immediate problem I have is that I want to...
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Monte Carlo Simulation Results Canceled
Hello,I was trying to do monte carlo simulation for one of my designs. But the results were canceled. Does anybody know what reasons could be?I ran the monte carlo simultion successfully for another...
View Articleinductor LVS and netlisting
Hi,My inductor cell schematic consists of nport model and a few pins, on the layout, there is has a special layer that blackboxed it from layout side during LVS.However, during LVS , the nport model...
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Missing Corner Setups ADE Explorer
I have a maestro view where I've created various corners. There are some views (notably older ones) where some corner setups do not show up in the corner drop down menu when in the Explorer view for...
View ArticleCan macro_name in "-va,define macro_name" be set in Corner Setup of ADE...
I'm currently maintaining multiple verilog-A views for one cell. I specify those views in Corner Setup of ADE Assembler. I'd like to consolidate them into one verilog-A view using `ifdef macro_name and...
View ArticleChanging names of multiple nets connected to a unique pin name
Hello all,My task is to change the net names for all the pins with a unique name. For eg. I have to change the net names connected to the bulk of the PMOSs to another name. The problem I am facing when...
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