Quantcast
Channel: Cadence Custom IC Design Forum
Viewing all articles
Browse latest Browse all 4897

Can macro_name in "-va,define macro_name" be set in Corner Setup of ADE Assembler?

$
0
0

I'm currently maintaining multiple verilog-A views for one cell. I specify those views in Corner Setup of ADE Assembler. I'd like to consolidate them into one verilog-A view using `ifdef macro_name and setting the macro_name in Corner Setup of ADE Assembler. I tried adding -va,define VAR("macro_name") in the command line options in Setup->Environment in the test editor, thinking I would be able to set the macro_name variable in Corner Setup of ADE Assmbler. But simulations failed to start if I use VAR() in the -va,define in the command line options. Is there a way to set macro_name in Corner Setup of AFE Assembler? I'm running simulations using Spectre.


Viewing all articles
Browse latest Browse all 4897

Trending Articles



<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>