Clik here to view.
Files getting locked
Hi,I am facing the issue with the simulation files (especially schematics) getting locked. I tried to create a new schematic mimicking the locked one and this too got locked somehow. I cant edit it...
View ArticleRecovering the deleted Symbol
Unfortunately, Somehow NMOS symbol of the built-in library got deleted, is there any way to recover it, I made a big schematic with that NMOS symbol, now the schematics are throwing warnings and...
View ArticleHow to undo an action in ADE Assembler?
Hi,I'm using Virtuoso ICADVM 20.1 and my question is quite easy. In ADE Assembler (or in Explorer) if I accidentally delete an output, an expressions or if I do an action that I simply want to undo,...
View ArticleClik here to view.
Removing the Visibility eye and the corner name from my results
HelloI would like to ask if I am able to remove the eye Visibility (Vis) and the Corner name from my result and only keep the signal name from the result shown belowI have tried to save by unticking...
View ArticleClik here to view.
AMS simulation error: "ncsim: *F, INTERR: INTERNAL EXCEPTION"
Hi,My virtuoso version is 6.1.8-64b. And my AMS simulator is "incisiv152hf".When I use the AMS to simulate the analog part and digital part together, some error happens.Actually, I used TSMC28nm...
View ArticleHow to plot waveforms in a particular order in WaveScan (ViVA)
Dear All,I want to plot the waveforms in a particular order in WaveScan after the simulation is done.How this can be achieved ?Kind Regards,
View ArticleClik here to view.
[ CCSChangeTrace]change default style and thickness of waveform/trace in ViVA...
Dear All,I gone through the link https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nWAKEA2&pageName=ArticleContent.I have used CCSChangeTrace("thickLine") in CIW. When I added...
View ArticleClik here to view.
comparison of two design points in a variable sweep
Hi, I would like to compare results of two points in a variable sweep from the same run in ADE-XL. The spec comparison feature in ADE-XL lets me compare design points from two different history items...
View ArticleWhat’s the best way to generate income via 3D printing?
Different ways to make money with 3D printingSell pre-made 3D prints on Etsy. …Offer a specialized 3D printing. …Start a 3D printing business in your local area. …Sell your 3D printing designs. …Start...
View ArticleApplying multi-bit VCSV files in analog virtuoso schematic
Hi all.Is there a way to apply a multi-bit VCSV file in analog schematic as stimulus?My file contents are like:;X, Y;Re, LogicBus;time, LogicBus;s,...
View ArticleError when plotting in adexl
Getting following error!sometimes when I am simulating, plots are available but other times it shows the below error with a blank graph window.ERROR (ADE-2404): Cannot find a setup database entry for...
View ArticleClik here to view.
Datasheet plots differently from Plot All result if using a Plotting Template...
Hi,I created a plotting template in Assembler and get nicely a subset of my output curves with nice re-arrangements acc. to my template. Note: Some curves have been deleted in the template to focus on...
View Article[INNOVUS] Automatic Placement with Hierarchal "Top Down" design?
Hi,Anyone know how to automatically place the module blocks for hierchal design?I've tried to use the "proto_design" command but I get an error (IMPFM - 760) stating that "The design has no flexmodel,...
View Article[INNOVUS] Performing top level implementation for hierarchal/block IC design...
I'm currently trying to perform the "bottom up" block design (hierarchal) approach in Innovus.It is very challenging to understand how to implement the top-level module.The User guide states the...
View ArticleHow to inspect older Assembler test setups e.g. regarding tran analysis details?
Hi,I know I can go back via Load setup to active.However, now this has happened: I run a somewhat modified transient noisie analysis in a test, and see it is now much slower than before. So I expect a...
View ArticleSimulation files for Circuit Optimization App Note
Hello,Does this app note have simulation files?I found other doc that has simulation files but it does not discusses global optimization.If there is any other doc that discuss global optimization and...
View ArticleClik here to view.
Label created in an unknown layer
I chose auto in creating the label for the pins.Now PVS shows that I created a known label in an unknown layer.I cannot select this label because the layer is unknown.I tried to find layer M2_47_TEXT...
View ArticleClik here to view.
How can I create multirow subrectangle part of Multipart path?
Here is the setup window. It results only one row of CA.Is it possible to have multirow subrectangle part ?
View Articlecaptab
In Spectre User Manual the fixed/variable cap reported with the captab analysis is defined as follows,1. fixed - stands for the device/wire parasitic capacitance2. variable - stands for coupling and...
View ArticleClik here to view.
Generating HSpice Netlist from Schematic in Virtuoso
Hello, I was working with a basic AND2x1 which I created using INVx1 and NAND2x1, all of the cells mentioned I drew in the schematic generated the symbols attaching to an existing library of...
View Article