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[INNOVUS] Performing top level implementation for hierarchal/block IC design ("Bottom Up" approach)

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I'm currently trying to perform the "bottom up" block design (hierarchal) approach in Innovus.


It is very challenging to understand how to implement the top-level module.


The User guide states the below:

"After block implementation, physical and timing abstract models (ILM/FlexILM) should be
developed for each block-level design that will be used in the top-level implementation. For the
bottom-up approach, create a top-level floorplan where block-level abstracts are referenced in the
top-level design."

Two questions:

1.) How to create ILM and FlexILM for a design?

2.) Anyone know what "top-level floorplan where block-level abstracts are referenced in the top-level design" means?


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