geomOr vs. geomCat
Hi there,We have to maintain some drc code and noticed that there is used geomCat() when logically geomOr() will make sense.Reading the the documentation we understood that geomCat() is almost the same...
View ArticleInclusion of Spectre analysis statements via include file in ADE: How to...
Hi,Spectre is very powerful regarding sweeps, but the ADE GUI has limited flexibility, e.g. I want to run such 4-dimensional sweep:sweepstb sweep param=Cm start=1p stop=25p step=5p {sweepstb2 sweep...
View ArticleCadence tool to analyse across-chip variations (distance-dependent mismatch)?
Hi,in 28nm and below the mismatch becomes quickly worse if you do not place matched transistors close together. In theory this can be treated in the statistical models by a correlation factor which is...
View ArticleApplying multi-bit VCSV files in analog virtuoso schematic
Hi all.Is there a way to apply a multi-bit VCSV file in analog schematic as stimulus?My file contents are like:;X, Y;Re, LogicBus;time, LogicBus;s,...
View ArticleAbout VCO design
Hi, I am designing VCO for ADC by using Cadence. But the problem is that i don't understand how to select Vpwl of VCO. kindly anyone can guide me how to select these.
View ArticleHow to inspect older Assembler test setups e.g. regarding tran analysis details?
Hi,I know I can go back via Load setup to active.However, now this has happened: I run a somewhat modified transient noisie analysis in a test, and see it is now much slower than before. So I expect a...
View ArticleSimulation files for Circuit Optimization App Note
Hello,Does this app note have simulation files?I found other doc that has simulation files but it does not discusses global optimization.If there is any other doc that discuss global optimization and...
View Articlemissing information of OCEAN created from ADE
I have meet the problem of missing options when generating the OCEAN from ADE(pss+pnoise simulation). Then i found the missing part in the input.scs created through ADE-Simulation-netlist-create....
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desVar interdependencies in maestro
hi,In maestro view (ADE Explorer) I have defined desVar "Vin1" which is a function of another desVar "Pin1".Pin1 = -40Vin1 = sqrt(2*50*10**((Pin1-30)/10))In HB analysis when I sweep Pin1 from -40 to 0,...
View ArticleNon-default path to 'si.env' configuration file when calling 'si' executable...
Dear allIn order to automate the generation of a CDL netlist from an OA schematic I'm invoking the si executable from the command line as follows:si -cdslib some/path/to/cds.lib -batch -command netlist...
View Articlesimulation not running when starting a new test simulation
Hi,I am using the version: 6.1.8.230 of cadence. I have different tests in my maestro view and when I try to start a new test simulation, different to one which is already running, it freezes after...
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Verilog A compact modeling
I have to model the VO2 device in Verilog A. But problem is that its I-V relation is very complexly related through temperature. These two equations are solved simultaneously to find out relation...
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Inherited connections and VXL.....again.
I thought I understood inherited connections, and i have no issues wrt simulation. But I am not sure of the procedure for having everything correct going from schematic to VXL.I have put together a...
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Save Assembler output setup to csv with "Description" column?
Hi,the csv import export is very nice, but it seems that if I enable the "Description"column, it will not be exported to the csv file.This is a pity, because a description is often needed if the...
View ArticleIs there a way to force plotting curves into the same plot?
Hi,e.g. I can get voltage noise vs frequency directly from noise analysis, but I could also run transient, and make a dft or psd plot. Now I want to overlay them, but ADE or ViVA defaults prevent a...
View ArticleHow to run simulations in Explorer/Assembler starting from a netlist?
The tool versions are below:Virtuoso IC 6.1.8-64b.500.15Spectre 19.1.0.541.isr14Hello,I need to netlist a circuit, edit the netlist and perform simulations in Explorer/Assembler using the modified...
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DAC Verification (ENOB, SFDR, DNL, INL, THD measure)
Hi, I am trying to characterize my 8 bit R2R DAC, I couldn't find DAC verification document on the Cadence Support, only ADC Verification. Some posts suggested using measurement->spectrum, but other...
View ArticleHow do I set valid layers on bootup of Cadence Virtuoso XL?
I would like to set my own custom list of default valid layers on bootup of Cadence Virtuoso XL. (IC6.1 and IC20)I never have write access to the tech file, so changing that is not an option.I want to...
View ArticleRemote-Host Simulation in ADE-L (or ADE Assembler) Does Not End
Hello, I have a few questions about the remote-host processing in ADE-L.I couldn't find this type of troubleshooting at the support so please excuse me even if I'm writing an unusual question.Since the...
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Changing the legend position in the Cadence results
Hello I am using the Cadence Virtuoso version IC6.1.8-64b.500.6I am facing a problem when trying to change the legend position from my result graph, for example if I want to change it form the default...
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