Hi,
in 28nm and below the mismatch becomes quickly worse if you do not place matched transistors close together. In theory this can be treated in the statistical models by a correlation factor which is a function of the geometric distance. I know two foundries which faced this problem, and they try to offer the IC design team improvements compared to the statistical models in older technologies.
I wonder, is Cadence offering something here out out the box? E.g. for post-layout simulations? Or in modgens?
The easiest case would be a layout of 3 MOS fingers in a row A-B-C. Due to larger distance A-C the stddev of VTa-VTc should be larger than the stddev of VTa-VTb, but in normal MC you would not see this effect unfortunately.
The issue is that e.g. the mismatch increases quite rapidly with distance, so the matching of 2 transistors 10um apart is significantly worse than for a layout with no spacing.
You can mathematically capture this in a covariance matrix with entries cab=cba, cbc=ccb and cac=cca, so in the simulation netlist such a matrix needs to be attached to the instances A,B,C for MC random number generation.
Bye Stephan