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Extracted Netlist Simulation Speedup?
Hi,I have a config view with verilog on top and an av_extracted view as an instance in it. I am using the UNL flow out of ADE Assembler (using newest tool versions).The av_extracted cellview is about...
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Montecarlo simulation not starting in ADE-XL
Hi,I have designed a schematic, which I simulated in ADEL version IC6.1.6-64b.500.8While running montecarlo simulation, I observed, the simulation did not even start. I don't know exactly where it has...
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[URI] Issues usign the scaleparam function in the URI (Unified Reliability...
I am implementing different aging models in the URI. I need to have the option to use both the appendage mode in the URI (write the results of the different models into a sub circuit) and the agemos...
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Automatic naming of ADEXL history items
Hello all,I'd like to try and automatically name my ADEXL history items using some information about the run. For example, instead of Interactive.0, I could envision having the date and time, and a...
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Hierarchy Editor: Instance bindings @ 2nd level of hierarchy depth
Hi all,Suppose I have a cell Top that instantiates two copies of a cell A (instances: A_I0 and A_I1). And suppose A instantiates a cell B (instance: B_I0).Should I be able to set the view...
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How can I use a vpwlf source with design variable for filename in AMS...
I found the same topic for the spectre simulator:support.cadence.com/.../cos;solutionNumber=11366978But actions discribed there not suitable for "AMS Unified Netlister".UNL take the cdf simulation...
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Cell only in schematic but not layout
Hi,Is is possible to have a cell that only exists in the schematic but not in the layout and still have it LVS clean?I give one example where I know that it works: noConn from basic.I give a couple of...
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Printing Corner Analysis information using VerilogA module
Hi,Is there any option to print the information of process corner using verilogA module?I am actually using a verilogA module to print some of my simulation result to a file ($fstrobe). But when I do...
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xmax and xmin are returning nil
Hi,I am trying to run xmax function on a derived signal, and even though I can see a clear maximum in the plot the xmax(z 1) is returning nil.The circuit I am using is a simple LC tank driven by a...
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ADE/Spectre Name Mapping with Extracted Views
I've been living with this issue for some time and was wondering if there was an elegant solution.When switching from using schematic based simulation to extracted simulation all of my save statements...
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scs files
Greetings, I am new to developing a compact models. I developed a compact model to a device in Verilog-A and I want to add statistical parameters to it. I looked at an older model developed by my group...
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VHDL-AMS simulation issue
I am using Cadence (ncsim?) to simulate the operation of a MEMS switch. In the code I have a generic time variable (called delay) that acts as step size (highlighted in the code snippet below). I use...
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GMRES solver convergence issue during PNOISE analysis
Hi,I am simulating phase noise for my VCO by running HB PSS followed by Pnoise analysis.During Pnoise analysis, I keep seeing following warning messages which make my simulation super slow:Warning:...
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Modification of the Extracted files (Through Cadence tools)
I am working on CMOS 65nm 10Lpe process from IBM. am using cadence 616 and I want to change the resistivity of M1. The extraction tool is Calibre from MG but the extraction files are encrypted so I am...
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How to know the most critical node that set my minimum transient time step ?
Hi all.I would like to know a way to find the most critical node that mostly set my minimum transient time step.Could some convergence report give me that information?Thanks
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Custom colors for waveform viewer and net selection in Virtuoso
Hello,Is it possible to modify the color sequence used for waveforms and nets in Virtuoso (6.1.6, 6.1.7) ?Does anybody have a good custom sequence (e.g., without invisible dark blue, or green already...
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Create VIA form disappears
Hello,I have been using layout XL and when I create vias in auto mode, the Create VIA form disappears and I cannot seem to get it back unless I restart virtuoso. Can someone please help me on how to...
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PhysConfig: Set physical parameters when using force descend.
Is it possible to set the physical values (lib/cell/view) when you use force descend?For example, in the physconfig of layout TOP, there is block A1. Block A1 contains blocks AA1 and AA2. I set a force...
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ERROR (LBRCXM-644): Bad return status from RCX script generator. 0xb
Quantus QRC works fine(except it double counts the parasitic of a Pcell) if I don't give Hcell list.Once I give HRCX cell list to avoid double parasitic extraction. I am getting below error.Kindly...
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Sheet resistance information
I have been trying to look for information about sheet resistance in my IBM 65nm 10LPe kit. I saw in some cases, sheet resistance information is in the technology file (.tf). Is that always the case ?...
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