VHDL-AMS simulation issue

I am using Cadence (ncsim?) to simulate the operation of a MEMS switch. In the code I have a generic time variable (called delay) that acts as step size (highlighted in the code snippet below). I use this variable inside a process and use "wait for delay". The code looks as follows:

begin
   break q1 => 0.0;
   break q1'dot => 0.0;

pr1:process
begin
  sene_120<= spoly_calc(q1,0.0,s_type120,s_inve120,s_ord120,s_fak120,s_data120);
  ca12_120<= spoly_calc(q1,0.0,ca12_type120,ca12_inve120,ca12_ord120,ca12_fak120,ca12_data120);
  wait for delay;
end process;

break on sene_120(2), sene_120(3), sene_120(4), ca12_120(2), ca12_120(3), ca12_120(4);

fm1==mm_1*q1'dot'dot + dm_1*q1'dot + sene_120(2) - ca12_120(2)*(v1-v2)**2/2.0 + fi1_1*p1;
r1==fi1_1*q1-u1;
f1==-p1;
i1==+((v1-v2)*(ca12_120(2)*q1'dot)+(v1'dot-v2'dot)*ca12_120(1));
i2==-((v1-v2)*(ca12_120(2)*q1'dot)+(v1'dot-v2'dot)*ca12_120(1));

I am having trouble running a transient simulation using this model. The simulation starts, and runs for a time which is exactly equal to the value of delay variable times 3000. For example, if delay is set to 100 ps the simulation will end at 30 ns. If delay is 500 ps the simulation will end at 150 ns. The error message I get is as follows:

Error found by spectre at time = 150 ns during transient analysis `tran'.
    ERROR (SPECTRE-16928): Cannot run the simulation because transient analysis
        has reached the maximum number of times allowed to approach minstep
        (within 5% of stop time or 5 us, whichever is less).
        Use the `max_approach_minstep' option to change the maximum number of
        times allowed to approach minstep and rerun the simulation.

When I simulate simple models written in VHDL-AMS, such as RLC circuits, the simulations run to the end without any problems. The interesting thing is that my MEMS switch model used to run perfectly on older versions of Cadence (around 2013-14). The Cadence version has been updated since and I cannot get the model to run. I had to make a few changes to the original model to just make the simulation start; for example the new version doesn't let me assign values to branch quantities in architecture declaration.

I am a novice at both VHDL-AMS and Cadence. Any help would be greatly appreciated!

Many thanks.