Cell only in schematic but not layout

Hi,

Is is possible to have a cell that only exists in the schematic but not in the layout and still have it LVS clean?

I give one example where I know that it works: noConn from basic.

I give a couple of examples where I would fine this useful:

1.) I created a "wire_model" cell that just implements first order parasitic estimations for long wires in my model. For Layout (incl parasitic extraction) this should just be replaced by a short.

2.) I have some dummy connectors which just route one pin to another. To avoid warnings and errors I just place a 0 Ohm resistor or a vdc with 0V in between. Clearly this should be ignored in layout because there is an actual wire

3.) My standard cell inverters have "output" as pin type but I need them to connect in parallel to achieve my desired strength. For example, I would have INV1<1:2>, INV2<1:10> etc.  In order to evoid warnings, I can also place them individually in the schematic and put a res with 0 Ohm between the outputs.

Thanks!