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Can't create a test in ADE L or XL
Hello:I did a new update and hotfix to Virtuoso Custom IC Design Environment version IC6.1.7-64b.500.10 and I am starting to get all kinds of weird errors.Whenever, I want to create a test in ADE L or...
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Sampled point inaccuracy in AMS simulation
Hello,I am trying to simulate a Verilog-AMS model of an ideal ADC, together with some Verilog-A and Verilog modules. Versions of the tools I use:virtuoso : IC6-1-6.64b.500.11spectre : 13.1.1.292.isr12...
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How to simulate the PSS+PAC, PSS+PSTB for Switched capacitor
Hi everybody!Hope you enjoy the good health!Now i am designing the Switched capacitor for Pipeline ADC. I want to check the loop stability for that circuit such as PSS + PSTB. I try to follow several...
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transient noise simulation with restart
Hi,I have a complex simulation where we expect flicker noise AND thermal noise to cause problems. So for a useful simulation I need the noisespetrum of 0.3 - 10MHz at least. The interesting timespan...
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vsin frequency precision, and tips for coherent sampling
I am doing basic SNDR simulations on the SNDR of a 10 bit SAR ADC. I noticed that at moderate input sinusoid frequencies, the SNDR starts degrading. To eliminate any errors in my simulation setup, I...
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Undefined function or variable 'cds_innersrr'.
Hello,For the below cds_srr function call, I am getting error in matlab. could you please suggest if it is a known bug or if there is any workaround available?Please let me know if you need more...
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phase noise sim for driven circuit with non-ideal input
My question is similar to the one in the following threadhttps://community.cadence.com/cadence_technology_forums/f/38/t/33153I also read some other posts on jitter and phase noise sim, but still could...
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Extract single net from layout
I've recently been spending some time trying to really understand how some power and ground meshes were done in a layout. I've been using probing in Layout-XL with the Net Probe Hierarchy Level set to...
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Virtuoso Spice In grouping instances
Hi,I am trying to import a CDL netlist into virtuoso. I am able to succesfully import the design but it is very hard to read the design. Currently I see that instances which can be generally grouped as...
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Error while simulating verilog-A block
Hai,I am trying to simulate one schematic which includes the variable capacitor (designed using Verilog-A). While simulation, I am getting some errors which I could not figure out.Can someone help me?...
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IQ cross-talk: simulation artefact?
Hi,I would like to simulate I/Q crosstalk in my system (and specifically assess whether I can use 50% duty cycle which is known to be problematic for I/Q crosstalk because two branches are used at the...
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How to store a value in Cadence using VerligAMS model
Hello guys,I have been looking for a storage element or something like that so that I can store the output value of my circuit (I have both verilog-AMS/A model of my circuit). Basically, after one-time...
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Frequency blocks within a sub-cell troubles
Hello,I lost my fully configured ADE L state already multiple times (until I found out why) because of the following issue: I put my frequency generator into a cell and instantiate it as an instance in...
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ahdlLib opamp model vref pin
Hi there, I try to use the opamp model from ahdlLib but there's a few point about the model I don't understand... 1. what are ibias and iin_max parameters ? 2. Is vsoft used for output clipping ?...
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Layout XL: how to set default options for Selection Protection?
Hello! Is it possible to set somewhere the default options for the Selection Protection feature in Layout XL (the ones under "Edit->Select->Selection Protection Options...")?Every time I open a...
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How to subtract a wire/path from a polygon
Folks,I am using Virtuoso (v 6.1.7). I'm making a lot of slotline structures in BEOL metals. I'd like to be able to simply draw a polygon on a given layer, then lay down a meandered wire of the...
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[ADE XL] Compiling verilog-A module
Hi- I am having problems in using ADE-XL due to the verilog-A compiling issue. In the beginning of simulation, the simulator re-compiles every single verilog-A block in the schematic which takes a lot...
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Floorplanner generate physical hierarchy
Hello, I have two questions about the generate physical hierarchy of the floorplanner tool.In "generate physical hierarchy", there are always some blocks that have Param Changed indicated as YES. They...
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Modifying extracted netlist for post layout simulation
Hello, I wanted to modify my extracted netlist and replace some transistors with their Verilog-a models. I have tried but it gave some error as "the cellview was modified..." (I cannot specify...
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Reg channel length in gpdk045
Dear Andrew,I am using gpdk045 MOSFET transistor in cadence Schematic editor. Here 45nm is the technology node or gate length ?. I require to know both the gate length (Lg) and effective channel length...
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