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Transient Simulation of AMS gives convergence error
Hi,I need to run a AMS simulation for a testbench that contains VerilogA block, functional block (Verilog) and Transistor level schematics. From the Figure below you can have a look:Here, The Input...
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what is the use of data.dm and constraint in each design directory?
Hi all, Normally when I try to "ls" a design directory I can always see these two files, both of which cannot be opened in a Virtuoso window (or even invisible for data.dm in the library manager)....
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Modify the resistivity of M1
I want to modify the resistance of the M1. Any idea how I can do that?ThanksSherif
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Confusion about DRC / LVS / Parasitic extraction tools
Hello,I am trying to install Cadence verification tools in my university but I am totally lost to choose packages.I will use GF8HP and GF8RF PDK through MOSIS.So, I installed Assura for DRC and LVS....
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Oversampling clock and data recovery for SerDes communication
Dear Friends, I am newbie to hardware design. I have a task to design a burst mode CDR. Typically it should have very fast frequency acquisition time. In my system, I have a 8 phase clock input. I am...
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Virtuoso Layout L: Show/remove hidden/old (metal) layers
Hi,I have a design which I migrated from a 10 metal stack to a 8 metal stack.It seems that the two "unsupported" metal stacks are still in the layout but I do not find any way to show and remove them....
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Not to remove instances whose terminals are connected together
Hi,When I want to run simulation in Spectre, I noticed that the instances whose terminals are connected together are being removed. Is there a way to keep them even if their terminals are shorted...
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Behavioral simulation of standard cells: How? (AMS and other attempts fail)
Hi,I am struggling for many hours with the following: The standard cells in my PDK have the views cmos_sch (transistor level), abstract, adms_vhdlams, verilog.I would like to perform basic functional...
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modeling device using Verilog-A and having convergence problems
Hi,I'm new to Verilog-A I am having convergence issues with a device I modeled in Verilog-A. When I have the device simulated in parallel with a time varying voltage source then the simulation seems to...
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Operating point parameters for BSIM-IMG devices
DC Operating point info for devices using BSIM-IMG model (mainstream model for FDSOI transistors) seems to contain only charge and capacitance information.BSIM transistor models have traditionally...
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Accessing spectre simulation results in an ocean script
Hi Andrew,I have a very weird problem. I have checked other posts but couldn't figure it out. Hence, I decided to post here.So I'm simulating a design in spectre simulator (an extracted netlist in...
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Generic signal names in VEC files
Hi,This question is based on https://community.cadence.com/cadence_technology_forums/f/38/t/37113 which explains that for AMS, the signal names have to be preceded by the name of my top level module...
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dcOp sweep
I'm interested in being able to *quickly* simulate some device small signal characteristics versus some parameter (design variable, temperature, etc). A dc sweep with dc operating point enabled in...
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ADE-XL doesn't pick up readic initial condition file/ How to properly pass...
Hi all,First of all, I am using Virtuoso 6.1.7-64b.I need to run transient corner sims for an analog circuit, and the first ADEXL run resultedin a lot of failures due to DCOp calculation failures. I...
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SPECTRE ASSERTS INFO: Invoking psf2ferret...Failed
Hi,I am getting following ERROR in ADEXL. It is a tran run.But, If I run it in the "test editor" or the "open debug environment" , the run completes properly and gives result.Kindly help me to...
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Don't want to save finalTimeOP.info
Hi,I'm trying to reduce the simulation data for a really large circuit. I'm going to do MC analysis and have to save family plots. I'm already saving specific nets. Also disabled saving all info files...
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Location of the hierEditor folder and any other [log] files
Can you please tell how to avoid ANY files to be created in my clean and tidy home directory, please ? I can't stand this... Cadence is the only software I use that does that.... Any other software...
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Memory characterisation using liberate-MX
Hi,Would like to know the exact definition of Retaining rise, Retaining rise slew parameters as they seem similar to Cell rise,Rise transition in .lib file.Can anyone state the exact difference between...
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VHDL-AMS library issue?
I'm trying to simulate a simple resistor implementation using VHDL-AMS in cadence. The VHDL-AMS code is as follows:library ieee, std;use ieee.std_logic_1164.all;use ieee.electrical_systems.all;use...
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resistor noise simulation by transient analysis
Hi,I am trying to run the simple example as depicted in the attached image, taken from Cadence's "Virtuoso Spectre Transient Noise Analysis" document, page 24.link is...
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