Behavioral simulation of standard cells: How? (AMS and other attempts fail)

Hi,

I am struggling for many hours with the following: The standard cells in my PDK have the views cmos_sch (transistor level), abstract, adms_vhdlams, verilog.

I would like to perform basic functional testing of basic, custom logic but the transient sim takes forever.

My hope is that abstract, adms_vhdlams or verilog could be used as behavioral model, speeding up the sim by multiple orders of magnitude. However, I have no idea what I am even supposed to do.

I tried the following:

1.) Use the HED to change the views of the cells to abstract and verilog and use Spectre, APS or XPS MS.

In all cases, references to the standard cells do NOT appear in the netlist. Subcircuits containing only standard cells become empty. Hence, the result browser does barely contain any signals and the one it contains are zero.
I am not sure if this is supposed to be the case or not.
Maybe the View List or Stop List needs to be modified? (I tried adding "verilog" to both without success)

If I set the views to adms_vhdlams, then I get an error like:

    ERROR (SFE-23): "input.scs" 22: The instance `I0' is referencing an undefined model or subcircuit, `C12T28SOI_LL_IVX4_P0(VHDLAMS_WRAPPER)'. Either include the file containing the definition of `C12T28SOI_LL_IVX4_P0(VHDLAMS_WRAPPER)', or define `C12T28SOI_LL_IVX4_P0(VHDLAMS_WRAPPER)' before running the simulation.

2.) Using AMS. My normal setup uses ic/6.17.701 and spectre/16.10.187; now I additionally load ius/8.20.006. I again use HED to create a new config and use AMS as a template. I select Plugins -> AMS and AMS -> Initialize.

Now weird things start already because I cannot close the HED any more, nor the CIW (I can only kill virtuoso). An attempt to close either just results in:

*Error* eval: unbound variable - _amsaIeConnectRulesInfo

In any case, I can continue by selecting opening the schematic/ADE L with the config and running the sim with AMS. However, then I get the following error in the CIW:

[...]
---------- End of netlist configuration information   ----------
INFO (VLOGNET-80): The library 'playground_ams', cell 'inv2_ams', and view 'config' has been netlisted successfully.

End netlisting Mar 22 00:19:51 2017
INFO (AMS-1243): AMS OSSN netlisting has completed successfully.
To view the modules, choose Simulation->Netlist->Display.
      ...successful.
create cds_globals...
*Error* IE cards generation failed.
      ...unsuccessful.
      
I tried the same with incisive/14.20.003; or even without either; same results.

3.) Use again HED and pick spectreVerilog as template. However, when opening ADE L, I cannot choose spectreVerilog as simulator. I do not know which configuration/package is necessary to make this visible.


Any ideas of either of these questions/problems??

Thank you!