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layer map file for GDS transfer to virtuoso
Hello all,I have a GDS layout previously designed in SoC encounter, I want to import it in Virtuoso but I don't have a layer map provided with PDK (I'm using Nangate Open Cell Library 45nm). I now have...
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Cadence Liberate: Path delays all zero in exported of verilog models
Hi there,I characterized custom cells for different corners and now want to create a verilog model for each corner. Although timings in the *.lib-file are totally different, path delay in all verilog...
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Generating a bit stream in Virtuoso
Hello all,I want to test a digital chip on Cadence Spectre using its extracted SPICE netlist from Calibre PEX. The chip has a bit stream of 128 bits as input and its outputs are: a digital bit stream...
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Can't open cells in hierarical schematic in Virtuoso
Hello all,I have a design in Cadence Virtuoso (originally designed in SoC Encounter using NangateOpenCellLibrary 45nm std cells), when I try to open any std cell in the design schematic, I get these...
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import physical verilog netlist in Virtuoso
I generated a physical verliog netlist for my design in Encounter using "saveNetlist design.v -phys -includePowerGround -includePhysicalInst". Here is the explanation of every attribute in this...
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Assura problems with feedthrough caps
Hi everybaby,I am getting extrange behabiour in assura. I have 2 digital blocks A and B sintetized independently and we have added prefixes A_... B_... to the corresponding subcircuits in to avoid...
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Spectre: use models on a per module basis?
Hello! Is it possible to tell Spectre to use different models for the same devices in different modules? Our design kit has standard and "PRE_SIMU" models (=include contact-to-poly caps and parasitic...
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Cadence Virtuoso: Import a large verilog netlist to cadence schematic
Hello all,I imported a verilog netlist for a layout previously designed in Encounter. When I try to open the schematic and hit check&save, I get these errors:Error: Net...
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layout dynamic selection accessibility?
Hi, in the layout dynamic selection assistant, is there an option to change the default text from light gray on white to black on white for all lines in the DSA (not just the selected line), for easier...
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Storing config of a cell in a file/cellview
Hi,Is it somehow possible to store design variables of a cell in a config-like cellview or file?Here is what I mean: Suppose I design a simple opamp for I which create a triangle symbol view and use it...
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BER test setup in cadence
himy question is regarding BER testing. I want to check the BER for OOK modulator/demodulator. I tried to find (in forum discussions) the setup/instances that may help to make setup for BER testing....
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Problem saving intrinsic parameters using save statement save NM0:all
Hello all,I know this has been addressed several times before as I've searched the forum before actually asking this question but I have tried the solutions but nothing seems to work. I'm trying to...
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How to make an ideal diode model for diode from analogLib?
I am trying to make a model and use it for ideal diode from analogLib library. However, I don't know how to modify the built-in potential (or forward voltage) of the diode. I tried to add VJ variable...
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QRC extraction problem
Hi all:I'm at QRC stage now where I have encountered this extraction problem:Cadence Extraction QRC - 64-bit Parasitic Extractor - Version 13.2.0-s451Tue Jul 22 19:35:08 PDT...
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anaName in OCEAN analysis not working
Hi,when I execute following commands:analysis('noise ?anaName "noise1")analysis('noise ?anaName "noise2")ocnDisplay('analysis)I see that anaName is saved and thus the 2nd analysis is overwriting my...
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how to find total capcitance of mosfet(pmos or nmos)?
what is the equation to find total capacitance?how to replace a capacitor by mosfet and how to prove them they are equal?
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Change a technology library into a design library
Hi All, Due to my mistake I set up a design library as a technology library and built quite some designs in it. Is there any way that I can change it back to a design library? I played with the...
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VIVA: how to disable automatic displaying of variables when hovering over...
Hi! I recently updated to IC617 and now in Viva a window appears with the variables values whenever I hover the mouse over the trace names. I've been trying to disable this feature with no luck (menus,...
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ADE-L: How to specify "options statements" for Spectre?
Hello! Trying to debug DC convergence issues I came across the "Spectre and APS Non-Convergence Debug Guide", where most solutions involve using "options statements". How and where in ADE-L do I...
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Create Vias: shapes, drawn areas
Folks,I am using IC6.1.7 (64b) on Linux, Layout suite L. I'm looking for documentation on the use of the Create Via dialog. Specifically, I cannot locate any information on using the "Shapes(s)" or...
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