Cadence Virtuoso: Import a large verilog netlist to cadence schematic

Hello all,

I imported a verilog netlist for a layout previously designed in Encounter. When I try to open the schematic and hit check&save, I get these errors:

Error: Net "v_CALCULATION_CNTR<7:0>" shorted to net "N5512,N5511,N5510,N5509,N5508,N5507,N5506,SYNOPSY S_UNCONNECTED__0".
Error: (DB-270004): Illegal bus reference - Can't tap "<N5507>" from net "v_CALCULATION_CNTR<7:0>".
Error: (DB-270004): Illegal bus reference - Can't tap "<N5512>" from net "v_CALCULATION_CNTR<7:0>".
Error: (DB-270004): Illegal bus reference - Can't tap "<N5509>" from net "v_CALCULATION_CNTR<7:0>".
Error: (DB-270004): Illegal bus reference - Can't tap "<N5508>" from net "v_CALCULATION_CNTR<7:0>".
Error: (DB-270004): Illegal bus reference - Can't tap "<N5511>" from net "v_CALCULATION_CNTR<7:0>".
Error: (DB-270004): Illegal bus reference - Can't tap "<N5510>" from net "v_CALCULATION_CNTR<7:0>".
Error: (DB-270004): Illegal bus reference - Can't tap "<N5506>" from net "v_CALCULATION_CNTR<7:0>".
INFO (SCH-1172): There were 8 errors and 0 warnings found in "NangateOpenCellLibrary key_expansion_KEY_SIZE0 schematic".

Moreover, I can see lots of unconnected wires like the attached picture



This verilog netlist was exported from SoC Encounter from a layout with no geometry or connectivity violations. 

Any suggestions ?

EDIT: the unconnected wires are probably due to some floating output pins of std cells that are not used in the design and I don't see errors complaining about them.