Hi everybaby,
I am getting extrange behabiour in assura. I have 2 digital blocks A and B sintetized independently and we have added prefixes A_... B_... to the corresponding subcircuits in to avoid problems when put together.
When placed together, they have independent power rails.
The LVS are clean if run independently but when they are put together i get a lot of parameter mismatch in cells made up by feedthrough cells from the std. library of the technology.
Suppose i have the cells feed1, feed2...feedn from the standard lib. When I open the LVS Debug Env. and i open the mismatches it shows that what is in the schematic feed2 is in the layout feed7 (for example). Like this many other similar.
I found out the ambiguities message during the LVS run as weel.
For me looks like assura is mixing the feedthrough cells. Since the feed cells in a block are all connected to the same VDD and GND the circuits match (instances, nets...) but the parameters not.
The autoswappin option is "off".
I hope somebody can elucidate some solution the problem or hint.
Best regards,
Manuel