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pcellEvalFailed when I change my cadence version
Hi Andrew,I am trying to run the post layout simulations for my project. Everytime I run Assura QRC it fails, I tried to change the cadence version from 6.1.7 to 6.1.5 to see if it works or not, but...
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Main Transistors from technology file are missing after QRC Extraction
Hi,I have run parasitic extraction on a simple inverter in a new technology that I have. After running the post layout simulation using Assura, the main transistors are missing in the analog extracted...
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Reliability analysis - custom models
Dear guys,I am trying to perform reliability analysis in Cadence Virtuoso, however the foundry do not provide AgeMOS models for process node, I use. So my question is: Is there please a workaround to...
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data.dm in cell, which view type is depend on it?
Hi, I am writing a design hierarchy analyser for data management, for example for check out, label or same check of design files. I will get all files from a design hierarchy. Is there any exists...
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Too many Point Sweeps (>1 M) for ADE XL to handle
Hi,I'm new to ADE XL, and not sure whether I am asking a dumb question..I'm trying to use ADE XL to sweep a parametric set of 10 variables, each having 5 values to sweep over. So effectively there...
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Subthreshold Standard Cells Characterization by Liberate
Hi there,I'm trying to characterize a standard cells library. I'm using tcl-files, based on RAK.Nwell of cells in this library does not connected to VDD but also to VDDNW, which could have other...
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Assura RCX fails
When I did RCX test at a certain design after passing DRC and LVS tests successfully, it failed.the following pictures for the log file (at the start and the end).However I designed previous designs at...
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LSSP Simulation for Floated RF Port is Reliable?
Hi,Hope you are doing well and stay fine. I am working on designing cross-coupled or differential RF Rectifiers using Cadence. Rectifiers are highly non-linear devices that cannot be charecterized by...
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Verilog-A block works with transient analysis but has no output with harmonic...
I have a sinusoidal voltage source written in Verilog-A (taken from this wikipedia page). I've pasted my slightly-altered code below.The component generates the correct sine wave output in a transient...
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Attached technology library is not showing up in an instantiated model
Hello,First, I would like to thank you so much for your help with the following question. I am trying to characterize an NCSU-CDK-1.6.0.beta. When I created a new library with one of their technology...
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Modifying variables during simulation
hi,Is there a way modifying the value of a variable as a simulation runs, like in AMS simulations?Imagine that I am running a transient simulation to find a trimming code and, without running another...
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Change Default Trace Type
I know you can change trace style/color/thickness through editing the following lines in .cdsenvviva.trace lineThickness string "fine"viva.trace lineStyle string "solid"Maybe it works for viva when in...
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Model files defined in .cdsenv for spectre are not loading
Hello,My understanding is that when launching cadence virtuoso loads different environment customization files in the following sequence:1. .cdsenv 2. .cdsinit I wanted to set up model files for...
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Virtuso Editor setting
Hi.This is a question about the Virtuso Editor setting.It is written as follows in the bar at the top of the Schematic editor.(like red in the figure)It is written in the order of 'Vrituso / Schematic...
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Preference to define bus bit format
Dear forum,Could you please let me know what is the preference name for defining bus bit format (angle bracket <> or square bracket []) during netlisting?Thanks,Norayr
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Changing the value of a Variable in Maestro every time a simulation is run
Hi,I would like to change the value variable (global or local to a test) every time a given test runs.I have created a local variable (numOfRuns), which is initialised to zero. Every time the test is...
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Modus IC Test DLI algorithm
Hello IC Designs.I want some information about the DLI (Defect Location Identification) algorithm based in Modus IC Test.I have some difficults to understand the branching for DLI.Standard cell ->...
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OP point print issue
Everytime i choose OP point print, ADE always goes back to the top of the design hierarchy, which is quite annoying. I need to go deeply many times to choose the device which i want to display OP...
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spectre fails to finish transient sims
Simulation abort with error and does not finish. Any suggestion on this ?Notice from spectre at time = 3.37543 ns during transient analysis `tran'. Newton iteration fails to converge at time = 3.37543...
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BSIM4 import into AWR
Hello,I am trying to import a cadence BSIM 4.4 model file (.scs) into AWR from a foundry PDK (built for Spectre RF). The parsing and symbol creation go through fine but it comes up with a load of...
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