Modus IC Test DLI algorithm

Hello IC Designs.

I want some information about the DLI (Defect Location Identification) algorithm based in Modus IC Test.

I have some difficults to understand the branching for DLI.

• Standard cell -> NET -> Branchs -> Segment 

also some fundamental concepts like:

• Fork Nodes;
• Internal Nodes;
• Tr. Terminal;

Any information are very grateful. 

Evandson.

A reference paper for my question: http://www.es.ele.tue.nl/~kgoossens/2019-lats.pdf