Calculation of noise multiplication factor (γ) for Ring VCO
Hello,In noise calculation in Ring VCO, there is a noise multiplication factor (γ). How to calculate γ in different technology.RegardsUpendra Ch
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Assembler Direct Plot add to outputs
Hi,An observation and related questions.I create an sp analysis in an Assembler test named ss. Add output expression spm('sp 1 1) and name it S11. Run simulation, then with cursor over the plot icon in...
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how to create a custom constraint group for Layout XL connectivity
In my current design setup, Layout XL mistakenly understand a dummy Metal _exclude_ (aka dummy block) layer to be connected to any overlapping Metal drawing shapes (with same Metal number) and thus...
View ArticleDownload older version QUANTUS211
Hi, I am a Ph.D. student, and currently, the university program only provides a license for QUANTUS211.However, it is too old, and I cannot find it in the support portal and cannot download it from...
View ArticlePin Creation Issue in Virtuoso Layout
Hi,When I try to create a pin named "vss2p7<0>" in the Virtuoso Layout view, I see the following error message:1. "Cannot create a net with name vss2p7<0>.2. dbCreateNet: Bus net base name...
View ArticleTwo stage CMOS OP Amp design)_error
Got stuck with the below error while trying to run a dc analysis for a two stage cmos op amp using freepdk15. Please help.ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view...
View ArticleDesigning a Two stage CMOS OP Amp using Cadence Virtuoso_hspiceD simulator
Hi,I am working on my academic project on 2 stage Cmos Op amp design and to run simulation for dc,ac and tran analyses using FREEPDK15 downloaded from this...
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Spice In with CDL netlist issue
Hi all,I met the following issue when I imported the CDL netlist with IC618.1. the symbol shows the total width is right imported from CDL netlist. but the property shows the default value which is...
View ArticleADE Model setup question
Hi,normally the ADE test setup contains many model files and picks certain sections like for NMOS5V the section MAX. And the ADE corner tool has a similar setup accordingly.To make the setup more...
View ArticleUnable to select pins in layout
I'd like to select some pins so I can move them. However, clicking on them, whether in the layout, navigator, or schematic, does not select them in the layout. All layers and objects are set to be...
View ArticleViva waveform save to pdf format not correct
When I try to save the waveform to pdf file in ViVa using save image button, the grid on the waveform is not correctly display. There is no horizontal grid and only vertical one. I have to change the...
View ArticleSorting list of version numbers
Have a list of version numbers. Example list("v-0.1" "v-1.0" "v-1.1" "v-2.0" "v-11.0" "v-11.2" "v-11.10")The example is a sorted list and the latest is "v-11.10". The lastest is determined primarily by...
View ArticleSelecting S-Parameter model file based on corner setting
I'm running corner simulations for an LC-VCO. I have different S-parameter model files for the inductor and I would like to include these automatically. I'd be happy to specify the file to be used in...
View ArticlePower Routing form won't select nets
Hello, I'm trying to route my power and ground nets in Layout XL using the Stripes tab on the Power Routing form. However, even when I have a net selected in the layout editor, clicking the "Selected...
View ArticleJunction Temperature Vs Ambient Temperature
Hi,Sorry if my question is too obvious. I just want to make sure that the temperature we set in corner definitions are actually "junction" temperatures and not "ambient" temperatures. Is that...
View ArticleSynthesizing Memory
I was wondering if one can explain the general steps of synthesizing memory in Cadence, I found this but didn't help much. memory synthesis RTL Compiler commands - Logic Design - Cadence Technology...
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the same extraction view got netlisted differently in 2 different test setup
Hi, there.I've got an instances i_1 (cell_1) in testbench test_1 and and i_2(cell_2) in testbench test_2.cell_2 has some minor differences from cell_1 but their symbols/pins are exactly the same (for...
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Defining Specifications for an Output
Hi all, I have a question about "Defining Specifications for an Output"If in the spec column I write VTEST which is bound to an ocean expression the evaluation is not working and give the following...
View Articledeepprobe to access verilogA
Hi, I wish to use deepprobe to access waveform of signal in verilogA. The signal is not a electrical signal, but a real number. Is that possible? Or is there anyway to transfer such a waveform to top...
View Articleskill function to get name of test defined in ADE assembler
HiI want to know skill function to get name of test defined in ADE assembler.In other word, I want maeGetExplorerTestName() euivalnet function for ADE assembler.maeGetExplorerTestName() only works for...
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