select from overlaps?
I have an M4 path on top of an M3 polygon. I have M4 selected in the palette, yet every time I try to add a path to the end of the M4 path, the palette switches to M3. I have checked that "select from...
View ArticlePower supply
Hello,I have designed an impedance matching circuit to adapt an antenna.I would like to test the entire schematic by inputting different powers through the input port, such as -10dBm or -20dBm, and...
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Duplicated Virtuoso icons in taskbar
Our systems are experiencing a graphical problem that makes all the Virtuoso icons in the taskbar to be a duplicate of one Virtuoso window.This is what we usually see:Note the schematic editor icon has...
View ArticleDEF input and output frim Virtuoso
When streaming in (and out) def from Virtuoso I need to be able to map a cell name based on the maskshift property in def.EXAMPLE 1:COMPONENT 1;- - U7 INV + PLACED ( 2000 2000 ) FS ;END...
View ArticleGet Hierarchy Editor to bind schematic and symbol views
Hi,I am looking for a way to get the Hierarchy Tool to allow me to swap in a schematic with a different number of pins than the original schematic, e.g., a cell with views 'schematic', 'symbol' that...
View ArticleHow to get around 'no library changes' in Config views?
Hi,I am working on testing modifications for a chip revision and thought I could use config views to pull in schematic cells, possibly of different names, from different libraries. But schematics in...
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How to save power signals in XPS MS simulation?
Because of the fast speed of XPS MS, I am using it to simulate my SAR ADC .But I find no power signal is saved after XPS MX whether I choose total, devices, subckts or all.There is no power information...
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How to save only the power information of certain circuits?
I am simulating a SAR ADC which has many parts. There are some choices in power save options. But even subckts choice is not flexible enough. It still save much power information I don't care.Is there...
View ArticleInput File for Vsource in Cadence Virtuoso
Hi,I am using vsource component from the analogLib library in my design. I have more than 400 instances of the same in my design & I am using it as a pwl with input given in a csv file. Therefore,...
View Articlehow to create lookup table VCVS in SPECTRE
I'm trying to port a design from PSPICE to SPECTRE and using the pspice_include directive but it is not parsing some of the PSPICE structures.EABC NODE1 0 TABLE { V(NODE2, 0) } + ( (1,4) (2,2) (3,1)...
View ArticleWhy VXL generates a pin with "1_" prefix?
I have a layout which contains several global supplies. One of them "v_hv!" comes over to the layout with pin name "v_hv!" but terminal name "1_v_hv!". This pin exists at several lower levels of the...
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problem with CDF
I have an issue in my schematic. When I select a transistor, on the side window next to parameters a warning says that a function : "tsmcCdfFormInitCB" does not exist.I checked CDF editor and it is a...
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Impedance matching
Here is my question,I know that I have to do impedance matching between stages like LNA and mixer, but is there any rule that I can decide where I should do matching and where I don't need to? Maybe...
View ArticleCUVHNF error in ams simulation
Hi,I would like to assign AVDD voltage to a real number in vams code by the sentence\\\analog beginAVDD_real = V(tb_xxx.DUT.ana_top.AVDD);end\\\Then I got the error info:xmelab: *E,CUVHNF...
View Articletransient temperature plot
Hi,I would like to plot transient temperature in viva using ams sim environment. The experience with spectre is, a non-connected net with name "temp". Its waveform represents tran temperature. However,...
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Only a functional file was created after using generate in Verilog
Hi everyone,I encountered a problem when importing Verilog in Cadence Virtuoso 6.1.8. I created an inverter (schematic and symbol) named "INV" using TSMC's 180nm package, and then I tried creating a...
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Attaching Hspice model to a newly defined cell view
Hello I have created a new cellview for a component as shown below but am having difficulty in associating the custom defined model with this cellview. The model is a Hspice subckt so I created a .scs...
View Articlevbit pattern
instead of defining a vbit pattern in a ADE library .scs file can the pattern be generated in the ADE schematic or as a parameter which can be modified during simulation?
View ArticleHow to include extracted output in your adexl simulation?
Hi,I have successfully generated spice output on quantus assura extraction and I got result in the form of .sp file. How do I include this extraction in my simulalations?Regards,Vishesh
View Articlemultiple power pads when global supply name used in sub blocks?
I have a design with multiple blocks, each block comprises multiple sub blocks and so on. In every cell/block I have used the global supply vplus! (among others). Now I have decided that I would like...
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