Only a functional file was created after using generate in Verilog

Hi everyone,

I encountered a problem when importing Verilog in Cadence Virtuoso 6.1.8. I created an inverter (schematic and symbol) named "INV" using TSMC's 180nm package, and then I tried creating a simple network with 4 of them connected in parallel using Verilog.

module parallelINV (input A);

genvar i;

generate

     for(i=0;i<4;i=i+1) begin: connect_invs

        INV I(.A(A));

     end

endgenerate

endmodule

However, after importing the Verilog file, only a functional view and a symbol view were generated. But the most important one, the schematic view, was missing.

Then I removed the loop and hard coded all 4 instances. This time Cadence was able to create the schematic view.

module parallelINV (input A);

INV I0(.A(A));

INV I1(.A(A));

INV I2(.A(A));

INV I3(.A(A));

endmodule

How do I make the for loop work?