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Designing a Two stage CMOS OP Amp using Cadence Virtuoso_hspiceD simulator

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Hi,

I am working on my academic project on 2 stage Cmos Op amp design and to run simulation for dc,ac and tran analyses using FREEPDK15 downloaded from this https://labs.ece.ncsu.edu/eda/downloads/downloads/687ac383-dd08-47eb-9150-f3f1af81be1b?expires=1682099952&signature=e8658191c60708cc15e73098a9eff1a959bb7512a3d5db36b3c20095dbaa82d8 I am facing this error tried many possibilty from reading the solutions form this forum but it would be great if someone can help with the exact issue that I am facing. Also the simulator is "hspiceD".

Getting schematic propert bagGetting schematic propert bagINFO (SCH-1181): "OPAMP Opamp schematic" saved.
Delete psf data in /home/isekar0315/cadence/simulation/Opamp/hspiceD/schematic/psf.
generate netlist...
Begin Incremental Netlisting Apr 14 21:55:05 2023
ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'hspiceD spice cmos_sch cmos.sch schematic', for the
instance 'I9' in cell 'Opamp'. Add one of these views to the cell 'idc' in the
library 'NCSU_Analog_Parts', or modify the view list so that it contains an existing view.

End netlisting Apr 14 21:55:05 2023
ERROR (OSSHNL-514): Netlist generation failed because of the errors reported above. The netlist might not have been generated at all, or the generated netlist could be corrupt. Fix the reported errors and regenerate the netlist.
...unsuccessful.


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