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RE: transient simulation accuracy
Hi AndrewI'm using transient simulation to draw the output wave forms of different LNAs, I know that Accurcy Defaults ( consevative, moderate and liberal ) manage the resolution of the wave form, but...
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Layout versus Schematic design issue
HiI am going to start with my layout design. I have a big amplifier with a biasing circuit. I remember from my past work the problem when I finish with my layout and running the layout versus schematic...
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Abstract physical information file (.LEF) of standard cell
Recently, I mainly research the achievement of digital standard cell library. For the given library cell layout, I'm planning to extrate the LEF file for floorplan and placement. But I don't know how...
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CSF search mechanism - load .cdsinit from $HOME even if its disabled in...
I have read the article "Cadence Application Infrastructure User Guide IC6.1.7" to understand the CSF search mechanism. Whilst playing around with the settings, I found that it still loads the...
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Running a stability analysis at multiple transient analysis time points
I have a script that runs a transient analysis and it saves the nodes at the initial and final time points. For both of those time points I'm trying to run a stability analysis, but for both stability...
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Sweeping different design variables at the same time within an (qpss) analysis
Hi,I'm using virtuoso ICADVM18.1-64b.83 and spectre 18.1.0.077.I have a port generating two tones, they have a power of P1 and P2 as design variables. I made those variables global variables in...
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Parallelizing simulation with a variable sweep in an analysis itself
Hi,I'm using virtuoso ICADVM18.1-64b.83 and spectre 18.1.0.077.I've set the max. jobs, in the Job-setup relatively high (28).I've set the High-Performance Simulation Options to APS and multi-threading...
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how to define different sweep variables for different test within the same adexl
Hi,It looks like sweeping variables can only be defined from "global variable" section (not "Design variables" from each test). In my case, transient and stb sim have different test benches, so I put...
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use outcome of one sim (w. post processing) as the input of next sim
Hi,I have a case as below:sim1: sweep code1 and based on output1 value (w. a threshold), decide which code1 to usesim2: set code1 to be the one chosen from sim1, and sweep code2.I've been doing this...
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Import .spef file in Spectre
Hello there! I would like to know whether (and in case how) it is possible to include into the spectre circuit netlist the .spef file, generated after the P&R, in order to simulate the circuit also...
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how to update connectivity reference hierarchically
Hello,when I opened layout of "A" and launched layout XL, the schematic popped was of "B". I did update connectivity reference to schematic of "A". But, the whole hierarchy of "A" is having...
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Running multiple AC sims during a transient analysis
I was looking for a way to run a transient analysis and at various times along the way perform an AC analysis. I found a way to do this via e.g.:analysis('tran ?stop "250n" ?actimes list("0" "250n")...
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shortcut to bring ADE with current schematic to front
Is there a shortcut or something to bring ADE to front (or to make it active or something like that I don't know how it is called)? The problem is that when multiple schematics and ADEs are opened at...
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VerilogA, one or the other parameter implementation
In for instance the port cell in analogLib you can enter for a certain signal either the Amplitude (Vpk) or the Amplitude (dBm). When one of them gets filled in, the other field blanks out.Is it...
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Unable to do some functions in the layout. Getting Errors
Hi, When I am trying to do some functions in layout the below errors are coming. Can you please help me to find the problem. To create pin: ERRORleHiCreateChoiceOfPin()* Field is "manualPinMode"...
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Setting TimeStep for Transient simulations : defaulting to ps
I'm tying to test my design using MATLAB. Specifically, I'm exporting time domain simulation data into MATLAB to do FFT in MATLAB.FFT requires coherently sample data. Therefore, my time domain data...
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Abstract LEF files with Abstract generator
Hello, everyone, I need you to help me deal with the error of Abstracting LEF files.In the process of "Abstract and Verify step" , I meet these error...
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"Assura has not been installed in this hierarchy" Error
Hello All,When I open Layout XL I receive this message from CIW*WARNING* dlopen: /eda/cadence/2018-19/RHELx86/ASSURA_04.15.115/tools.lnx86/assura/lib/64bit/libavview.so:...
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Show all drivers for a particular signal at a particular time in ncim
Hello,The problem is expressed in subject: does exist some technique that allow to show all signal drivers at a particular timeThanks in advance.
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Renetlisting after change of design variable
Hi all,I have a design which uses a few design variables (e.g. the amplitude of a port). When I change the value of the variables in ADE L between simulations, this change is not detected and the...
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