Hi
I am going to start with my layout design. I have a big amplifier with a biasing circuit. I remember from my past work the problem when I finish with my layout and running the layout versus schematic then if I have an error it will be hard to identify and or more difficult to correct it. The difficulty will rise exponentially if the correction needs to be redesigned for some parts in the middle of the layout.
Is there an option in cadence layout tools where I can run the LVS at any level of my layout design by excluding the remaining of the circuit. Just as an example I would select to layout only the differential pair transistors then I run the LVS, if LVS is ok then I continue to layout the next transistors and so on until I finish with the circuit. Such an option will be also useful to simulate the circuit at each added part of the layout.
I have tried similar kind of trick by dividing the circuit in many parts and put every part in symbol and layout it individually, after then I connect the whole symbols to build back my circuit, but this method is mostly like designing digital system from different cells. However, in digital cells are mostly unique cells where one can connect them easily, not like the analog circuit cells.
Thanks