Matlab cadence integration setup
Hi everyone,I am using cadence ICADV 12.3 and ADE XL for my simulations. I am trying to setup integration between cadence and Matlab to do my post simulation processing. I saw some tutorials online but...
View Article[Virtuoso] What is wrong with my RC transient simulation ?
Hi, I am trying to do a simple RC transient simulation in Cadence virtuoso. Please see the circuit below:I am trying to see the transient current and voltage of the capacitor being charged,however I...
View ArticleError in running HSPICE NETLIST using cadence virtuoso ADE L
Hi,I am trying to go through a tutorial 'FreePDK15:Analog Artist with HSPICE' from the following link. https://www.eda.ncsu.edu/wiki/FreePDK15:Analog_Artist_with_HSPICE#Saving_the_HSPICE_NetlistOnce I...
View ArticleVerilog-A Oscillator Phase noise
Hi,I have an verilog-A oscillator model which has a certain jitter. Using transient simulation I can get the total period jitter which matches the input jitter to the model. But I would like to have...
View ArticleCalcVal
Hi Everyone,Can someone point to some place with documentation about calcval: how it works, what's for, examples?Regards
View Articlefunctional mismatch of pre and post layout simulation results
In cadence virtuoso, with scl pdk 180 nm technology, the schematic is correct and is showing the correct pre layout simulation result using ADE L. After designing the Layout, there is no DRC error...
View ArticleParameter sweep in layout and running extraction
I'm using ICADV12.3-64b.500.21 with Calibre interactive v2018.4_25.17.From the schematic view it is easy to perform (parameterized) sweeps of device parameters and do simulations.I would like to do the...
View ArticleTransient simulation crashes SPECTRE181, APS
Hello,I have the following problem: My transient simulation crashes with this error message in the simulation output log:Internal error found in spectre during transient analysis `tran'. Encountered a...
View ArticleVIVA calculator dnl&inl
Hi,I try expression below. It could not work.dnl(abs(dac_out_DC) 0.625m ?mode "auto" ?crossType "rising" ?delay 0.0 ?method "end" ?units "lsb" ?nbsamples (256/VAR("dac_step")))but it works when I...
View ArticleHow to access data in info databases in PSF directory?
Hi Andrew!I was checking for information regarding instance parameters for my study purpose. In the psf file, there are many files with extension ".info". These .info files are binary. Is there any way...
View ArticleDynamic nodesets on DC Sweeps
Hi all!I'm having difficulties to find the desirable OP point during a DC sweep with a comparator that use a amux a resistor string to generate the hysteresis. The simulator find most of the time a...
View ArticleADE Explorer Variables to VerilogA Parameter Arrays
With reference to this post:https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/20875/how-to-pass-array-of-parameters-through-cdf-down-to-a-veriloga-codeIt seems like the GUI of...
View ArticlePSS Harmonic Balance Analysis, unexpected results
Hello, I am simulating a readout chain with the harmonic balance in PSS analysis. I receive so many warning on imelt and Vgs voltages of transistors but when I see the time-domain signal, there is...
View ArticleERROR [SFE-874]:'Unexpected end of line' while running a .scs file generated...
Hi, I am trying to simulate a basic inverter circuit using spectre. I have generated a netlist file. when I run it, I am getting the following errorERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib"...
View ArticlePlotting VerilogA String Variables
I have written a VerilogA testbench that runs a few automated tests using IC6.1.7 and SPECTRE171.I thought it would be useful to plot the current test phase as a string on the waveform as this could...
View Articleuse output signals from other circuits as input for simulation
I have two circuits A and B. I simulated the circuit A and has some waveform results. Can I save those some of the waveform and use it as a input signals to simulate in the circuit B?
View Articlehow to set netSet to connect power of sub-cell to top level cell to pass lvs
Hi All,I have a top level schematic name cell_top. In cell_top I have 2 instance name cell_A and cell_B. Cell_A and cell_B are generated by innovus play and route flow which don't have any power pin....
View ArticleOperating Region of transistors
Hi everyone,I have a circuit with couple of subcircuits inside it. I was wondering if there is a way to have a print of operation region for all transistors inside all subcircuits to make sure that all...
View ArticleMonte Carlo simulation of noise contributions using SpectreMDL
Hello,I'd like to obtain values of noise contributions in the circuit for each Monte Carlo run.I was able to make Spectre output total noise for each Monte Carlo iteration into a file, but no luck with...
View ArticleADE Assembler - Define IF statement with multiple results arguments (vector)
Hi everyone,Could someone provide some insight how to define a global/design variable in ADE Assembler Maestro in terms of an IF statement, but instead of passing just one value after evaluating the IF...
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