Quantcast
Channel: Cadence Custom IC Design Forum
Viewing all articles
Browse latest Browse all 4889

how to set netSet to connect power of sub-cell to top level cell to pass lvs

$
0
0

Hi All,

I have a top level schematic name cell_top. In cell_top I have 2 instance name cell_A and cell_B. Cell_A and cell_B are generated by innovus play and route flow which don't have any power pin. Inside of cell_A and cell_B the power net name is vdd! and vss! which inherit from vendor lib. On the cell_top, cell_A power  connect to vddl_lvt and vssd_lvt and cell_B connect to vddl_mvt and vssd_mvt. 

Layout is connected  properly but schematic can't since there is no power pin to cell_A and cell_B. I heard that we can connect it using netSet but I don't know how to to that . Can someone please help 

thanks 

Nhumai 


Viewing all articles
Browse latest Browse all 4889

Trending Articles