Library Manager display settings
Hello,I defined in Library Manager -> Edit -> Display Settings, some custom settings.How could I change them? Is there an editable configuration file in which they are saved?Thank youBest...
View Articleline continuation symbol for the cds.lib file
Hello,is there a line continuation symbol for the cds.lib file?Thank you,Aldo
View ArticleHow to find frequency for ring oscillator in Monte-Carlo analysis?
HiHow to find frequency for ring oscillator in Monte-Carlo analysis?thanks
View ArticleVirtuoso ADE Explorer/Assembler problem with load balancing system (type SGE)
Dear All,I have come across problem when trying to run jobs over load balancing system of SGE type while using Virtuoso ADE Explorer and/or Assembler (IC_6.1.7.715 aka IC6.1.7-64b.500.15). I have no...
View Articlenot_gate verilogA model in ahdlLib
The following lines are in the verilogA model of "not_gate" in ahdlLib. I have marked 3 lines as A, B, C.@ ( initial_step ) begin... <<deleted lines>>endlogic_in = V(vin) > vtrans; //...
View Articlefilter_sg in dyn_floatdcpath check
Hello All,I was exploring dyn_floatdcpath check in spectre. Came across a filter , filter_sg. But couldn't make it work at all. Any suggestions on how to use this filter?
View ArticleParametric Analysis - Random Values
Hi Friends,In the ADE L - parametric analysis, I could see options to sweep the variable in the linear/logarithmic/auto etc between the specified min and max values. But is there any option to provide...
View ArticleVerilogA model Monte Carlo Simulation - Histogram Curve
Hi,I want to try monte carlo analysis for circuits defined in veriloga model. So I have started with the ahdlLib" "res" cell example provided in the cadence support ((Link) . I have done the following...
View ArticleInconsistent "PSD" results between MATLAB & Cadence Calculator
Hi all,I have been trying to verify the variance (total power) of a random normal distributed noise source.The noise source model has been modified from the noise_src in ahdlLib but with...
View ArticleTechno via construction constraint for overlapping vias
Is there a via constraint supporting following DRC rule: Minimum extension of Mx beyond the overlap area that VIAx and VIAx-1 are fully or partially touching.So the metal extension must be larger...
View ArticleHow to set conditional tests in ADEXL to avoid running tests not needed in a...
Hello All,I am currently executing a pre-trim and pos-trim checks for an oscillator using ADEXL and Montecarlo sampling with the PSS tool. In the initial pre-trim I ran the simulation bench at 27degC...
View Articleerror in checking lvs test with calibre tool
hi i'm trying to apply lvs test to the layout of my circuit that is a transimpedance amplifier which uses 4 spiral inductors .the problem is when i try to check lvs it gives me an error as following...
View Articlemore pin name and net name checking at check and save
Hi,How to add in more custom checking during the check and save? For example, we would like to forbid some specific keywords (say, verilog keywords in a list file) for pin names or even wire/net names....
View ArticleLeakage current and Leakage power
Hello,I'm designing an SRAM cell for my project using 45nm technology.I would like to calculate the leakage current and the leakage power. Could anyone elaborate the steps that I need to follow?
View ArticleVerilog-A model and temperature in AC-Sim
I have a verilog-a model that is dependent on the simulation temperature, using the "$temperature" variable.The temperature value changes vs. corner simulations. The simple model gives a voltage in...
View ArticleMonteCarlo simulation is taking much longer time than expected
Dear All,I am simulating Monte-carlo of 100 runs on a test-bench with PSS/PAC analysis.The standalone PSS/PAC run takes just 30 seconds.But when I run with Monte-carlo, it is taking much longer time...
View ArticleVeriloga parameter expression
In veriloga documentation I have seen examples where one parameter is used to set the default of another parameter in the same module.When I tried this I found it didn't work in ADE/spectre. A simple...
View ArticleADE XL netlisting error (some schematic components are blank)
I have a simulation that isn't working with ADE XL - whenever it netlists parts of the netlist have no connections. I am using standard cells with predefined connections in them and have some...
View ArticleColor of "tool tip" text
Hi,I seem to have inadvertently changed the color of the text of the "tool tip" (the bubble that shows up when you hover your mouse over a button in the GUI, for example when you hover your mouse over...
View ArticleConverting Waveform data to list or vector using ocean Script
Hello,I am using "cross function" on the output waveform in cadence which is giving me a 2D vector( Multiple rows and 2 columns).wave=cross(v("/OUT" ?result "tran") 0.6 1 "either" t "time" )I want to...
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