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Syntax for device checks associated to just one type of simulation
Hello,I am creating a number of device checks in ADE using a separate file (devcheck.scs let's say). I wondered if there was a way to specify that a check just be performed against one type of...
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Cadence Custom Layout for beginners -RF IC design
Cadence Custom Layout for beginners -RF IC design It's the first time that I am creating a layout for an LNA design at 35Ghz. What should I read or watch for understanding how to create the layout,...
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leHiCreateVia
Hi, I am facing an issue while placing via in layout. when I press 'o' in layout window it will execute 'leHiCreateVia' function and gives me an option to create via. If I create via this way by...
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Verilog-A import variables from file
I do have a lot (really a lot) of different variables in my Verilog-a model, likereal var_00=0001;real var_01=0002;...real var_FF=0003;As the huge number of variables make my code unreadable and...
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dynamic parameter in SpectreMDL
Hi, Basis: there is a need for me to change the temperature within the transient simulation. I followed the post as linked below, and got it working in Spectre from ADE...
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FILL* on schematic unbound LVS error
I have imported my .cdl netlist file which contains all the standard cell connection information along with FILL and ENDCAP cells. Normally due to unbound error, I have to run LVS with...
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How could I assign IO type during " Create Pins from Labels" option
When I import .gds from INNOVUS , there is no pins but labels. So I have to use "Create Pins from Labels" tool to place pins. But all the pins IO type are "inputoutput". How could I define IO types so...
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problem with lvs in calibre
hi i'm trying to apply lvs test to the layout of my circuit that is a transimpedance amplifier which uses 4 spiral inductors . i encountered some problems . it gives 16 error which 4 of them is saying...
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saveNetlist option changing view to functional from schematic- Innovus to...
Hello All,I am performing an LVS run using Calibre. For this, I imported the stream/gds file and the the verilog file after my backend flow (Innovus). The .v file was converted to a SPICE netlist...
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Back Annotation of Segmented Resistors
We have a situation where a single resistor device is placed in a schematic. Then in layout, the designer segmented the resistor into two series resistors. The device has a CDF parameter called...
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Retain settings in Visualisation & Analysis Tool
Hi,In the Visualisation & Analysis Tool, I split up some of the waveforms to different stripes or I move some of the waveforms to an additional subwindow. However when I start a new simulation, all...
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modgen: best way to change device m-factor?
Hello,The following question does not have a clear answer for me after reading some of the Cadence documentation on modgen. I have been using modgen only recently and find it very useful, but wondered...
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*WARNING* Connection to MACHINE failed. No route to host
Hello,when I want to start PVS in the Virtoso Layout Editor I get the warning *WARNING* Connection to MACHINE failed. No route to host in the CW. (MACHINE=name of the machine on which I started...
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RE: Electromigration SEB flow FIT calculation
Hi All,Heard about SEB(Statistical EM Budgeting) flow to measure FIT(Fails in Time) for interconnects. It includes joule heating of inter connects as well as self-heating. Anyone know how to do this in...
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Virtuoso XL: Pins are preventing Analog Adjust Cell Sides from adjusting...
I'm currently using Virtuoso XL version IC6.1.7-64b.500.6 to do custom analog layout. I'm fairly new to IC6, and I do not have any corresponding Cadence schematics for my layout.I have three pins...
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Getting started with modgen
I am trying to get started with modgen. A friend of mine gave me some information provided by him but it refers to an old version which is quite different from mine. Do you know where can I find some...
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Two Pins on the one wire
Is there a way to place two pins on a wire without creating a short?I'm trying to make a four port transformer PCell.Each winding is just a metal path and I can't see how to have input and output pins...
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Preventing the config view from defaulting to AMS
When I load the config view it defaults to the AMS simulator and not spectre.I've set the environment variable "asimenv.startup simulator" to spectre but the config view overrides it, is there a way of...
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how to customize right click menu in adexl data view window and add save option
Hi, I am using adexl to run analog design. In general, there are many functions in the right click menu in the data view window, when you right click your test name. At the same time, I find the...
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Parameterization feature of ADE-XL does not work with Schematic Pcells
Hello, I am using ICADV12.3-64b.500.17 and I am trying to parametrize a design using the variables and parameters window in ADE-XL, and I am facing two different issuesI noticed that sweeping some...
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