not_gate verilogA model in ahdlLib

The following lines are in the verilogA model of "not_gate" in ahdlLib. I have marked 3 lines as A, B, C.

@ ( initial_step ) begin
... <<deleted lines>>
end

logic_in = V(vin) > vtrans; // line A

@ (cross(V(vin) - vtrans, 1))  logic_in = 1; // line B
@ (cross(V(vin) - vtrans, -1)) logic_in = 0; // line C

• What is the reason for having both line A and lines (B,C)? Latter seem to imply the former unless the inputs don't cross the threshold at all during the transient simulation.
• Would it have been enough to have line A within @(initial_step) begin  ... end?
• If line A is indeed redundant, does having it slow things down because it is continuously evaluated?

Other gates have similar codes.

Thanks

Nagendra