Veriloga parameter expression

In veriloga documentation I have seen examples where one parameter is used to set the default of another parameter in the same module.

When I tried this I found it didn't work in ADE/spectre. A simple example:

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`include "constants.vams"
`include "disciplines.vams"

module test_param(n1, n2);
inout n1, n2;
electrical n1, n2;

parameter real myres = 1k;
parameter real twores = 2*myres;

analog begin

I(n1, n2) <+ V(n1, n2)/twores;

end

endmodule

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When I tried simulating this in a test bench, ADE added myres to the list of design variables to be set.

If I try running without setting a value I get an error:

Error found by spectre during hierarchy flattening.
ERROR (SFE-1997): "input.scs" 14: I0: parameter `twores': Cannot run the simulation because parameter 'myres' has been used but no value has been assigned to it. Assign a value to the parameter and rerun the simulation.

Is this a bug?

Thanks,

Robin