Issue with autogenerating multiple Verilog-A views in same cell
Dear Cadence Forum,I've created a Python script that autogenerates Verilog-A models for discrete capacitors that model their non-linearities due to DC bias degradation. The python script attempts to...
View ArticleTransient Simulation
Does the dynamic parameter allow changing only one parameter during .tran? Is there a way to change multiple variables using the dynamic parameter option?
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ADE-XL Mismatch Monte-Carlo Simulation Issues
Hello,I'm a student and I'm trying to figure out how to use the Monte Carlo simulation built into Cadence Virtuoso's ADE-XL simulation tool for personal research. Right now, I am just trying the...
View Articleuse events in spectreMDL expressions
I am exploring spectreMDL. One of the feature I would like to use at the moment is to stop a transient simulation at a given condition. My current DUT needs to be configured, and it takes different...
View ArticleThey are the top defenders in NBA2K23
The game has also grown significantly over last year's version the NBA 2K22 game clocking in at under 120 GB across the various platforms.NBA 2K games crammed with plenty of great content, but not many...
View ArticleModelling and design of an optical receiver
Dear all,I am working on the design of an optical receiver consisting of a Transimpedance amplifier (TIA), a two stage variable gain amplifier (VGA) and an output buffer.I am initially modelling both...
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Post-simulation error
Performing a tran pre-simulation of the circuit and being able to perform the simulation without any problems.After extracting calibre for post-simulation, the simulation keeps reporting the following...
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Only 6 digits are displayed in Move/Stretch options menu
For example, when I input value lager than 6 digits, for example 1000.055,it will turn to 1000.05 if I click outside the column, but the actual value is entered as what I actually input (from...
View ArticlePSS for PLL loop
I am runnnig PSS for PLL with VCO and divider being ideal. I see that PLL loop is converged in PSS. Loop bandwidth is 10MHz. When I give -100dBc noise in reference signal source to PFD, at the output...
View ArticleDesign Intent questions
Hi,we plan to adopt this feature, and have the RAK, but several questions popped up on how to use it:1. There is a feature to define a circuit half, to let it match to the other half. This is nice, but...
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i want to read (2 dimensional array) , not only the first line
i have text file (3x3) as shown below in the screenshot , and when i wrote the below code, it only reads the first line, however i need to read all number ( 2 dimensional array).the first line will be...
View ArticlePnoise on signal at multiple of the fundamental
Let's say I have a clock circuit where the lowest frequency is 1Ghz, but the I want to measure the jitter on a 2Ghz signal. This means that the main signal will have two cycles in the PSS simulation,...
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PVS LVS 'number of fingers' and 'm-factor' calculation
Is there a way to find number of fingers / fold/ finger count and m-factor together in a multi-finger device in PVS LVS using the set up attached?
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How to silence noise of different part of circuit by a parameter in Transient...
I want to evaluate the noise contribution of different part of the circuit in transient simulation. Currently, select the option "Noise Contribution" in Transient Noise will help, but it means I have...
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Simulation fails to start when using variable1=calcVal()+variable
In my explorer, I have an 'ac' testbench and an 'tran' testbench. I am using the ac simulation to quickly get the circuit bandwidth, and adjust the input frequency in the tran sim based on the ac...
View Articlesah like functionality required
Hi There,I want to implement a block using verilogA which can sample input analog voltage at very first edge of the clock and and retain if forever. sah does similar functioanlity but it updates output...
View Articlehttps://community.cadence.com/cadence_technology_forums/f/custom-ic-design/38...
As explained in https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/38053/display-current-view-in-window-title-bar, it is possible to customize the order of properties of the...
View ArticleMC test dependent on pass/fail of previous MC test
Hello.I am trying to create a 2 step test simulation for a Test Screen for customer sample units. I want to a) tell production how many units to expect to test to generate a certain number of good...
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sim error when running sp simulation
Hi all,I have hard times troubleshooting the following error:I just desire to run a sp simulation and therefore I defined some ports for then assessing the SP results.from the error it looks like I...
View ArticleHow can I change the virtuoso editor for read-only text files?
Changing editor = "<my favorite editor" from CIW or .cdsinit seems to only set the text editor for edit mode. Is there a way I can change the read-only editor as well?Thank you!
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