PSS for PLL loop

I am runnnig PSS for PLL with VCO and divider being ideal. I see that PLL loop is converged in PSS. Loop bandwidth is 10MHz. When I give -100dBc noise in reference signal source to PFD, at the output of vco, I am seeing 1/s (integrator) behaviour even below the bandwidth of PLL. Ideally, within the bandwidth , there should be flat noise from reference source. I turned off all noises except reference voltage source. How to interpret this behaviour at VCO noise?