Dear Cadence Forum,
I've created a Python script that autogenerates Verilog-A models for discrete capacitors that model their non-linearities due to DC bias degradation.
The python script attempts to create multiple verilog-a files and the symbol. My goal is that is should be possible to just load in the cell view in the library manager and then work.
The Python script generates multiple verilog-a views for the same cell. I've tried to follow the adequate file structure that Cadence require for the Library Manager to acknowledge the cell. (creating a folder the symbol with the relevant files, e.g. symbol/ and for the veriloga view e.g. veriloga/).
The desired structure is:
CELL: {{capacitor_name}}
VIEW: symbol (consisting of the symbol files)
VIEW: veriloga (consisting of the veriloga.va file and the master.tag file)
VIEW: veriloga_rc (consisting of another version of the veriloga.va file and a master.tag file)
VIEW: verilog_rlc (consisting of another version of the veriloga.va file and a master.tag file)
The script functions well for the view named just "veriloga". After I import the library with the library manager, I can open the veriloga view with the text editor from the library manager and when I save, the netlist.oa and data.dm files are generated automatically. Great.
But for the two other views, which are veriloga files, but not named "veriloga", the library manager cannot find it. The CIW window gives the following error message, when I try to open these with the Library Manager:
*WARNING* ddsServOpen: Unable to find the master file for capacitor_models/GRM21BC71E106KE11/veriloga_rc.
I know that you get a warning message, when you go file -> new --> Cell View and create a veriloga TYPE, with a cell name different from veriloga, but the library manager simply asks you if you want to use veriloga TYPE for the file.
The reason for the multiple veriloga views is because I want to easily switch between the different complexity of the views using a config file later.
My fear is that there is some reference stored in the binary data.dm og netlist.oa files, that I need to be correct.
Any suggestions on fixing this. I really don't want to sit and create the view names for the veriloga_rc and veriloga_rlc manually with the library manager and then copy the veriloga code into these files. There must be a better way!
If it is relevant the python script is located on github here:
https://github.com/muheicdesign/generate_capacitor
Thank you in advance.