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Virtuoso Constraints SKILL code: correct my cstFindFirstConstraint syntax

I'm trying to get the ConstraintID of a particular constraint in the tech file foundry CG:orderedSpacings(( minOppExtension "METAL5" "VIA45" (0.020 0.11) 'ref "Mn.EN.1 Mn.EN.2" ))my skill code:techdb =...

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trapezoidal ringing with spectreX

Hi,I try spectreX to speed up the simulation. With "preset" = MX/AX, the tran waveform displays trapezoidal ringing. With "preset" = CX, the ringing disappear, but paying more time and license. Is...

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Dc operating point info with spectre -X LX

hello Tool Version : ICADVM20.1 -64bI am running a very basic Dc operating point info simulation on my circuit.( top level ; resonably big)  Iam using spectre-X with preset LX option along with APS-DC...

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datapoints/memory array

HI everyoneI have two questions herefirst: how to convert a set of datapoints (stored in a text file) each having ten bits (b0.....b9) to be the input trigger of ten pulses sources (V0..V9) with timing...

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How to run multiple analysis (ac, stb) in one test and make it work in...

Hi,I find the useful post about how to run multiple same type simulation in one test:   LinkThe basic idea is write a specific .scs file and load it in the assembler bench. In the result browser, a...

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Digital Vector File/How to Change the Voltage Level 3 Times

How / Can I change the Vih value of a single bit in the vector file up to  three different voltage levels in the Tabular datai.e b[0] has voltage = 0.8 V for the first period (0-10ns) b[0] has voltage...

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Errors when simulating parametric sets of more than 3 parametric sets in ADE XL

[ Used version : Virtuoso IC618 ]I'm currently trying to simulate a parametric set with ADE XL, but I'm having a problem.I understood how to create a parametric set in ADE XL through help documents and...

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Spectre simulation can not run when use Liberate to characterize the T22nm IO...

liberate version:LIBERATE 17.13.076spectre tool:IC61/616ISR6: mmsim15.10.627-ISR12when use liberate to rek T22nm IO cells, spectre simulation will report error likes  blews: LIBERATE - SYSTEM ERROR -...

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How to plot temperature vs time in Viva?

Hi,I am using veriloga and cds_set_temperature to make T varying vs time. I could plot the internal variable to get T = f(t), but I wonder if there is a more direct way? I am using icavd 20.1.500.22...

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How to save ADE Explorer setting and results

Hello I am using Cadence version 6.1.8 64 bitI am working with ADE Explorer for my circuit simulation. I would like to ask you how can I save a certain simulation setting with the obtained result so I...

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STT-PMA MTJ

I want to build NAND/AND gate using LIM architecture with MTJ/CMOS. so i first build the write circuitry . when i calculate the power it is in Megawatt. Normally I saw power in nano or micro watt. I am...

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Cadence Viva Plots - customizing default legend display

In Viva plot, by default legend entries are Vis & modelFiles. How to change it to History to appear by default?

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converting transistors in a schematic from analogLib to technology library

Hello,I want to generate a general schematic that can be handled in all techs and then in each tech I want to convert the transistors from analogLib to the technology transistors. Is there any way to...

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Symbol Editor: Moving Axes to Background Such That Graphical Elements are not...

HiIn the symbol editor, I like to enable the axes display such that I can easily align the origin of the symbol to where I like. But the axes cover graphical elements, in particular the rectangular...

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Can I prevent switching from Assembler to Explorer with single click?

This happens too often accidentially, and can take minutes for large setups. Is there an option to get e.g. a confirmation dialog? Or that you need RMB instead of a simple click?Bye Stephan

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Automatic check and save in Assembler/Explorer??

Hi,I remember doing check & save for the schematics has been partially automized In Virtuoso. So I remember, if it is needed and you forgot it, then after pressing run you got a reminder, and even...

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Characterizing Transmission gate based cells for liberty file

Hello,I want to characterize a pass-transistor or transmission-gate-based standard cell (e.g., MUX or XOR). As the pull-up and pull-down networks are not connected to Vdd and Gnd, like standard CMOS,...

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how to plot dynamic parameter "temp"

Hi,I have defined a dynamic parameter "temp" in a tran simulation. I wish to  make an expression in the output setup. However, temp seems only available in the data browser as a variable, which is only...

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STT-MTJ

Can anyone help me to plot R-V curve  of STT-MTJ in cadence . As I am new to cadence, how to obtain the same from dc analysis. I am attaching the schematic. I am giving a pulse of -1 to 1v. . When I...

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Calculator does not show updated value for a design variable

Hi allI have a PLL for simulation and I set the stop time to 7us. However, I usually stop the simulation once the PLL locks (e.g. at 6us).I started the simulation with some design variables (in...

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