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PCB Editor Allegro Copper Etch is Highlighted
I am not sure why all the layers have copper etch highlighted and also some pins.
View Articlepss+pstb simulation of boost converter when it is unstable
Hello, now I am designing current mode boost converter.So i did schematic the circuit blocks i need, and then i ran transient simulation to see the output voltage.But it seems like oscillation at...
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QRC substrate_connection -device_list option
In QRC it is possible to change how substrate/well connections are made using the substrate_connection command.With the device_list option it looks like it is possible to connect to the nearest well...
View Articlehow to set the env hed.checks?
Hi,I would like to define the env variable as below in CIW,envSetVal("hed.checks" "libListCheck" 'toggle nil t nil)I also tryenvSetVal("hed.checks" "libListCheck" 'toggle (nil t nil))but it always flag...
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difference between "temp" & "tnom"
Hi,What is the difference between "temp" and "tnom" in the dynamic parameter option?BR
View ArticleUsing 'm' multiplier or vector/array notation for MonteCarlo simulations
Hi all (first interaction here),I have a general question regarding MonteCarlo simulations. Should there be a difference in the result of a MonteCarlo simulation if I use the 'm=100' multiplier on a...
View ArticleNumber of Harmonics in PSS analysis to determine the maximum time step
How can I control the maximum time step in the PSS analysis by adjusting the number of harmonics under 'Output harmonics' section in PSS analysis window for autonomous circuits?
View Articleway to set timer length in verilog-A
Hi,The syntax of timer in verilog-A is timer(startTime, period). I am wondering, if there is any way to limit the ending time of timer or limit the number of periods?BRThanks
View Articlemaestro runs complete counter disappears
In a maestro once a run is started a counter appears on the bottom frame of the window showing the number of runs complete x/y and a percentage counter. Sometimes this does not appear after a run start...
View Articlemaestro spectre parallel jobs reduce as total jobs neared
If you may have a large number of corner spectre runs and select 10 Max Jobs, you will get those 10 runs in parallel until you near the end and the parallel jobs starts to reduce down to 2...
View ArticleMatlab cadence integration setup
I am using cadence ICADVM 20.1-64b and ADE Assembler for my simulations. I am trying to setup integration between cadence and Matlab to do my post-data simulation. I have followed the link below to...
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Installing a Cadence in batch mode
I am having a problem installing cadence in batch mode. Below is the screenshot of the error. I would appreciate any sort of help in this regard.
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Voltage jump in transient noise simulation when reading data from file
Dear all,I want to include a voltage noise source with a custom spectrum given in a file in a transient noise simulation. For illustration purposes, I made a minimal example as shown below. It merely...
View ArticleConvolution in frequency domain?
I want to perform a simulation where I've a PRBS input (time-domain) that is passed through a port with a s-parameter file (frequency domain) and obtain the output in time-domain but the simulation...
View Articlehow to include the verilogA content in the netlist
Hi,I am new to verilogA. When i run sim with verilogA model + spectre simulator, the netlist only include a link to the .va file. Such a link is instant, meaning it only show the current content of...
View ArticleUsing "libName" as a function argument
No issue. Just commenting on an observation.Developing a script that parses cells in a library and one of the functions in the script takes the library name as an argument.I was using "procedure(...
View Articlesynthesizing Verilog code in Cadence Virtuoso
Hello,I would like to ask you how I can synthesize a logic gate from my Verilog RTL description. For example, I have made a simple 4-bit counter in Verilog and I have tested the functionality with the...
View Articlespecify editor for ADE Explorer documents
Is there a way to specify what editor will be used for opening a document in ADE Explorer? I have an Ocean file (.ocn suffix) and when I open it, it is coming up in gedit and I'd prefer xemacs. The...
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passing global variable to ADE output
Hi all,in ADE assembler I defined a global variable named "active_port" which value is changing from corner to cornerThe ADE test is made up by a DC+ SP simulation. In the ADE outputs I defined a bunch...
View Articlesetting temperature by veriloga via cds_set_temperature and make it work for...
Hi,according the Cadebnce suggestions I made such kind of VA module:// VerilogA for bhvLib, vctemp, veriloga`include "constants.vams"`include "disciplines.vams"module vctemp(in); parameter real tupdate...
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