synthesizing Verilog code in Cadence Virtuoso

Hello,

I would like to ask you how I can synthesize a logic gate from my Verilog RTL description. For example, I have made a simple 4-bit counter in Verilog and I have tested the functionality with the AMS simulation, it is working fine but now I want to translate this code to logic gate in Cadence Virtuoso and do the layout of it.

I am using Cadence Virtuoso version 6.1.8-64b

Thank you in advance

Regards