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How to see the properties of two cells together which are in same layout window.
Actually what i want to doI have two similar cells layout in which I have created many parameter (repetitions of contacts and vias, and stretch lines). In one cell I have set the no. of via and...
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Standard Cell Libraries (Basic)
Dear Sirs.I want to make my little Standart Cell library.I want that in my library there must have been not only gates but also triggers.How to choose the necessary and sufficient set of standard cells...
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save expression to file in ocean-xl
Hi,It seems the ocean script generated from ADEXL is able to cover all functionalities from the GUI. However, there's one thing I have yet figured out and wonder if anyone can kindly offer some...
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stitching results of two transient simulations
Hi,This might be a simple question for those who are skilled in spectre but it seems I can't figure out how to do the following. I want to run two transient simulation, the second one starting from a...
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tdnoise or pnoise?
Hi,I'm simulating a test bench consisting of a crystal oscillator, followed by several inverter stages that act as buffers.I want to simulate the phase noise at the output of the last buffer, and...
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problem simulating a sub-circuit (spectre model) with ade
Hello,I have a spectre model for a layout only component (no netlist) and I want to simulate it along with my rest of the circuit.I followed the guidelines in...
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Monte Carlo analysis with vprbs
Hi,i have setup a testbench that contains a vprbs source. When running a monte carlo analysis with e.g. 200 points only the first point differs from previous started runs.All other points are equal...
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How to avoid compiling Verilog/sytemVerilog views every time you netlist (AMS)?
Hi,I would like to know if is possible to avoid compiling the Verilog/sytemVerilog views every time you generate an AMS netlist in ADE-L (based on a config file with a sytemVerilog template).The...
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cds_get_analog_value or cgav is not correct
Hi, I'm using Incisive 13.20 . I'm having a strange case that for $cds_get_analog_value(hierachy,"flow") , the result is a delay value of previous time step.For example:Time = 1e-06; I = 10e-06; I_cgav...
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MDL: create a new waveform and save it into a wavefile
Hello,I have this MDL file:alias measurement mdltest { run tranprint fmt("%g %g\n", xval(voutp), yval(voutp)) addto="sample.txt"export real divided = V(voutp) / V(voutn)}run mdltestand I run it with...
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VerilogA vs. built-in device models
Hello, I've been using verilog-A to model devices for quite sometime and I wanted to ask what differences are there between the user define model (written in verilogA) and a built-in mosfet model, for...
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creating custom cell
Hello,I want to create some layout only custom IP blocks(inductors/balun etc.,). I can draw their layout and modify them according to EM simulation results. During the modification time, I am...
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Any way to format the print statement in spice?
Hi,I'm new to OCEAN/MDL..I need to print all the voltages and currents in the circuit for further text processing. I don't know the nodes and terminals beforehand.SPICE syntax .print v(*) i(*) works...
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Error running DRC on Assura - "The Assura DRC Run Failed"
Hello,I've recently installed the Cadence software in my institution's computer, I'm running IC6.1.7 on a CentOS 7. When I tried using the Assura package (ASSURA41) for a DRC run , it failed. The Log...
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Assura DRC deck in PVS.
The system admin at my university informed me that ASSURA has been replaced with the Physical Verification Package this year. I had some questions which I was hoping someone from Cadence support could...
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Phase Margin Calculation
Dear all,I am creating some expressions on ADE-XL (under Outputs setup) and I am having problems to do a simple phase margin calculation, since sometimes the phase starts at 180 deg and other times...
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Transient simulation of a crystal oscillator
Hi,I'm simulating a 80MHz crystal oscillator, so it is a circuit with an high Q (around 80k).I want to run a transient simulation of this circuit, and I'm experiencing that the results are a lot...
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PSS and number of harmonics in crystal oscillators
Hi,I'm simulating a test bench consisting of a crystal oscillator, followed by several inverter stages that act as buffers.I want to simulate the phase noise at the output of the last buffer, and...
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LVS without schematic
Hello,I'm working on cadence virtuso Layout L or XLCadence version ==> cadence/ic/06.16.050Calibre version ==> mentor/calibre/2017.1_25.22I do only layout, I' drawing only elementary structure...
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Placement algorithm that used in SOC Encounter
Hi all,I am relatively new to the Encounter tool. I am using Encounter v6.2 to place a simple design.I have a question about the Place & Route Algorithm that used in this software.I want to know,...
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