Hello,
I'm working on cadence virtuso Layout L or XL
Cadence version ==> cadence/ic/06.16.050
Calibre version ==> mentor/calibre/2017.1_25.22
I do only layout, I' drawing only elementary structure such as MOS or CAPA so on then these structure wiil be electrically characterized. Therefor, you can understand, I don't do schematic.
I did any check on my layout as Design Rules Check (here all is perfect).
Then we are using Layout versus Schematic to check a short/node between different layer ( Ex : Metal1 (layer) pintext (purpose) and Metal2 (layer) pintext(purpose)), let's have few minutes to details this operation.
We assume that a semiconductor wafer includes a plurality of chip areas having circuit elements, a scribe line area for defining the chip areas, and a plurality of test element group (TEG) modules
The TEG modules are group formed on the scribe line area. Each of the TEG modules has test transistors, a common source pad, and a common body pad.
A global gate pad is commonly connected to gates of test transistors in the test element group modules.
Global drain pads are shared by respective test transistors in the TEG modules.
So to check the right connection between my PADS and the Gates, Source and drain (i.e physic connection for example metal connection), on one side we put the label (label = pintext) on the gate and on the other side we put a label on the pad, we repeat this operation for the source and the drain.
We are using LVS tools to retrieve a report about connection, we check the report to see whether label gate is connected with label Pad or not in other words we check if there is a short.
Now my issue with this method, I can't be able to detect a "right short" from "wrong short" , sometimes I layout complex structure with lot of connection and in my lvs.report several node results are shaked in one paragraph/section, this makes the analysis difficult.
Hereinafter an example of LVS with "right short" ( no complex structure ;) ):
Here in my extraction results I can see that my diode is connected with the PAD1 and the bulk is connected with the PAD2.
Hereinafter an example of LVS with "right and wrong short" ( no complex structure ;) ):
Here in my extraction results I can see that my diode is connected with the PAD1 and PAD2 and the bulk is connected with the PAD1 and PAD2.
In this case it's easy to detect the problem but when the structure is more complexe it's very complicated...
We know that LVS tools is not suited for this task and I 'm working on another method more safety but maybe you know a better solution ?
Thank you.