problem simulating a sub-circuit (spectre model) with ade

Hello,

I have a spectre model for a layout only component (no netlist) and I want to simulate it along with my rest of the circuit.

I followed the guidelines in "https://community.cadence.com/cadence_blogs_8/b/rf/archive/2009/01/07/tip-of-the-week-how-to-simulate-a-subcircuit-netlist-with-spectre-in-ade"

in which i created a symbol, copied the symbol view to spectre view and modified the cdf for the block/sub-circuit.

Now, when I instantiate the block in my testbench where it is connected to other blocks and components from analogLib, the simulation fails at the netlist level with the following error

Begin Incremental Netlisting Sep  5 15:39:23 2017
*Error* eval: unbound variable - simVerilogFlattenBuses
End netlisting Sep  5 15:39:23 2017
ERROR (OSSHNL-514): Netlist generation failed because of the errors reported above. The netlist might not have been generated at all, or the generated netlist could be corrupt. Fix the reported errors and regenerate the netlist.
      ...unsuccessful.

However, if i remove all the other components except the block from my testbench then simulation passes, ofcourse the simulation itself is meaningless but aleast it generates the netlist with my component displayed as below

I2 (net3 net2 net01) test_bp

Can someone shed some light on what I am doing wrong?

Thanks

BR