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RelXpert Error with intermediate file input.p1
HelloI am trying to run RelXpert for the first time and I get the following error in the rxprofile.log file :...* Netlist file: profile.cfg* Starting time: Thu Sep 14 16:37:56 2017** Command Line...
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Help in HB Simulation in an autonomous circuit with driving signal input.
Hi,I'm simulating an oscillator with a source input to kick-start the oscillation. I tried to plot the the frequency of the output signal Vs. the control voltage. But I have read several posts saying...
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Passing different CDF parameters values to instance arrays
Hi,I'm trying to pass different transistor lengths/widths to an array of nfet devices MN0<2:0>. I tried passing "[100n 200n 300n]" in the length field of the nfet property window as suggested...
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cds_get_analog_value for inherited connection
Hi,Could I use cds_get_analog_value to measure an inherited connection port? More specifically I need to measure the current at an inherited connection port using cds_get_analog_value.Thanks,Hoang
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unable to load .sdb file
Hello,I've got one weird issue with cadence. I am in the ADE-XL environment. When I try to load the corner setup by clicking on 'Click to add corners', Load Corners GUI shows up. However, it won't show...
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virtuoso won't start -- core dumps
We had a Linux maintenance down over the weekend. Linux severs were patched as part of the maintenance down. checkSysConf output prior to patching/maintence down is included below. A new file system...
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ERROR (ADE-3023)
Hello to everybody,Recently I have begun working with Cadence Virtuoso 6.17. When I want to perform an ADE-L simulation I obtain the following error in the CIW:ERROR (ADE-3023):Cannot run simulations...
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Launching simulation on Remote machine in ADE-L, ADE-XL
Hi,I would like to launch my simulation on a Remote machine.. I would like to know the procedure and the settings required to launch simulation on remote host in ADE-L and ADE-XL.Thankyou.
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Noise Simulation of DAC+VCO
Hi all,I have to do noise simulation of DAC+VCO. So I am doing Pss-Pnoise simulation. For DAC, there is witch capacitor circuit, and input of the DAC are clock signal and trim bit (according to which...
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CCVS in subckt probing one level up?
Is there a particular syntax which can be used for the probe= part of a ccvs instantiation in spectre that would let me refer to something one hierarchy level up?What I am looking to be able to do is...
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n-tones sine wave
Hi AllI have a rookie level question. I am trying to run a transient simulation and I need a "multi-tones sine input". Like Vin=A1*sin(w1*t)+A2*sin(w2*t)+A3*sin(w3*t).I find Vsin but that only have one...
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Cadence Variables setup
Hi teamI have a quick question concerning variable design in cadence. I am an experienced ADS user but new to Cadence. I realized a major difference between ADS and Cadence concerning variable setup.In...
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vcvs Impedance Dips in Frequency
Hello,I am trying to create a near ideal voltage buffer using the components of analogLib. I have tried using vcvs and other controlled sources. All these perform the function correctly but always have...
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Incisive Digital Design Workflow
Hi,I have IC6.1.5 with (I think) Incisive 12.1. I work with AMS 0.18um technology.I want to implement a digital circuit which I would make using Virtuoso, implementing gates "by hand". However, I want...
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How to import values for a long list of design variables?
Hello,I have a standard logic gate library that has all the different logic gates with ppar for passing the nmos and pmos (width, length, nf) values to the symbol level (an inverter for example).So...
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Core filler not getting inserted below vertical power stripe
I am using Innovus Implementation system V15.20 for my design flow, My design contains custom made cells for which lib and lef file has been generated manually (using liberate and abstarct tool...
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Cadence ADE L can't simulate output for longer simulation time.
I'm trying to design a 10MHz clock in virtuoso. But when I'm using ADE L for transient simulation, output graph do not show proper result depending on simulation time and this simulation time. for...
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Plot PM versus a swept parameter using parametric analysis
Hello everyone,I am trying to plot Phase Margin versus a parameter that was swept using parametric analysis. I have tried to plot this using the direct plot but unfortunately it didn't plot what I...
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ADEXL parallel tests
Hi,I am aware of starting multiple simulations in ADEXL (Options -> Jobsetup). However, I wanted to change some circuit variables and run multiple parallel tests, but not all permutations. For ex,...
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detecting process corner from within verilogA model
Hello,I need to create a model of a current source in verilogA but the value of the current depends also on the process corner. Is there a way for the verilogA model to detect what corner the...
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