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Nested equations in ADEL
Hi, I want to compute the time elapsed between the falling edge of two signals. I've used cross() to get the time at which each event occurs, and it works. The problem is that when I try to compute the...
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Invalid probe for a .measure statement where node also exist as port in one...
Hello All,Consider the following node in a .measure statementV(segio.segio0.controls.xcontrols_opt/RDWEN_T)Now when1) RDWEN_T is signal above statement works.2) when RDWEN_T is port is gives invalide...
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LVS shows "StampErrorMult" error
I'm designing a current source layout in Virtuoso 6.1.6.-64bMy circuit contain mim capacitors, NWELL diffusion resistor along with 1.8V NMOS and CMOS. when I ran LVS, it provides this three error:>...
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IC617 layout slow in VNC
We recently updated from IC616 to IC617 (IC6.1.6-64b.500.14) and have felt like the interactive performance of virtuoso layout-L, even in read-only mode, has suffered. We exclusively access the eda...
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String variable as node name in mdl file?
Hello,I wonder if it is possible to substitute a node name in mdl file using a sting variable. e.g.:alias measurement meas1 {input string myNodeName = "comp0.Q" export real vQ=V(myNodeName)@1n}Thanks...
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ERROR (VACOMP-1008)
Hi!During simulations I have found these two errors in the log file (I'm trying to simulate a verilog-A component):ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file...
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Body Connection for 18nm process finfet
hi everyone,I want to design layout by finfet 18nm process but I could not find tap cell ( well tap & substrate tap).So I want to make own tap cell for body connection but I don't know layer type...
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How to open Cadence using C35B4 design kit
Hello guys,I have used C35B4 design kit 4years before, but I forgot how to open Cadence. Anyone knows?For example, -csh-(what is here?)-virtuoso & (or ams?)Thanks in advance.Best regards，UUinfini
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CDF parameters constantly revert back to prior settings
So I routinely create libraries where we release it as an IP, with only layout, symbol, spectre and auCdl views for the customer to access.The spectre and auCdl views have CDF parameters such as model,...
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Ambiguity Threshold in PVS-LVS
Hello all,I am working on a project where use a number of std filler cells. In LVS, these filler cells gave parameter missmatches, with the warning of ambiguous cells in the design.So I adjusted the...
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Controlling combinations in Techgen / Techgen for Quantus-FS only?
I'm trying to understand what options, if any, I might have for controlling what different combinations of layers, widths, and spacing are used in a "Techgen -simulation" run. This is EXT17.12. Also...
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Copy adexl view without history
Hello,I would like to have 2 adexl views and I would like to create a copy of the first adexl view without the History. The reason is that I want to simulate at the same time with two different...
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error in AMS simulation
Hello, I'm stuck with an error in my simulation that prevents me to see any results.I have a system with one Verilog block, plus I'm using the extracted views (with Calibre Pex) for my analog blocks. I...
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LEF generation from abstract is missing class,symmetry, origin information
HI ,I am trying to generate LEF file of an abstract (top level cell: TOP_CELL). Eventhough LEF is getting generated it is missing the following...
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Creating all pin symbol containing inherited power\ground connections
Hi,I am working on Virtuoso, version IC6.1.7-64b.500.4. I am using inherited connections in the schematic. AFter parasitic extraction, I observe that the inherited connections are missing in the...
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Distributed Processing Library command line
I've been looking in to how I can get multiple machines involved in a Techgen run. I read the DPL User Guide and it suggests some command line utilities for verifying the DPL config file...
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Gain of a Charge Pump in Phase locked loop
Hi,I made a charge pump for 1GHz PFD up and down signal pulses. I am interested in finding out the gain of Charge Pump. Can anyone guide me the good reference or some idea about its procedure?Thanks,
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change instance name in schematic
It is a very simple question, it seems that I can't change an instance name by "q" it in schematic window. I have to go to the property editor and change it there. For instance, I placed a resistor R1...
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gpdk045 vth at dcop is not same as model spec
Hi, AndrewI have checked the gpdk045 model report, it's said the vth is obtained using constant current method, the intercept current=Icon*W/L (Icon=1e-8A for 1.1V device and Icon=1e-7A for 1.8V...
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How to determine Scaled-sigma sampling (SSS) Number in high-yield estimation...
I am running high-yield estimation (HYE) simulation for custom SRAM design in Virtuoso 6.1.6 ADE XL. The simulation circuit is a critical path which contains representative cells and wire delay models...
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