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Auto PR Boundary Alignment in Custom Layout
Hi,I am doing custom layout in Virtuouso & and for that purpose, I'll define some designs (as per standard cell rules) and instantiate them in the upper level layouts.Now, when I instantiate any...
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ERROR (OSSHNL-109)
Hi,No matter how many times I check and save, every time I try to generate the netlinst I get the below error. Please help me solve this. Cadence Virtuoso version: IC6.1.6.500.1ERROR (OSSHNL-109): The...
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Node capacitance difference between captab and AC analysis
I want to measure the effective capacitance on a particular node of my schematic ("/net1").I tried two methods:1. Using the captab nodetonode option in DC analysis, reading the "/net1" to "/net1" total...
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Virtuoso crashing on executing mgc_rve_load_setup_file command for big layouts
HII am trying to execute the following 'mgc_rve_load_setup_file' command in CIW for a batch of cells.( mgc_rve_load_setup_file command is used to generate calibre view from a pex netlist). For that I...
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Create a simple abstract view from layout
Hello,I want to create an abstract view from an existing layout. This abstract view must contain only pins and the prBoundary.Is there a simple way or tool in cadence to do this?
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spectre: subcktprobelvl and the reliability of Monte-Carlo results
Dear Cadence forum,while experimenting with my netlists with respect to the performance of spectre simulations, I found this forum post saying that reducing the parameter value of subcktprobelvl can...
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Abstract generation : Warning : Design contain zero-pin terminal.
I'm using Virtuoso Abstract Generator , version IC6.1.6-64b.500.14 . When trying to run step pins for the cells, I got this warning:> *WARNING* (ABS-12042): Cell NAND2X1: Design contains zero-pin...
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LVS mismatch
Please help me with this issue, When I ran LVS in my design i see this message, I am tried to solve this issue.( Design FinFet 18nm design process).Please help me fixed this issue.
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Virtuoso XL: how to remove instance pin from net?
I'm using XL layout on a layout that was initially created in L and has no connectivity source.Most of the layout work for this cell has been completed in L with no connectivity, so, I'm just using XL...
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ADE-XL extension using OCEAN-XL
Hello,I am trying to run an OCEAN-XL as an extension using ADE-XL. The way I've been trying to do this is by right-clicking on the ADE-XL output list and "add OCEAN script", but I find that it is not...
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VLS-XL Assign instance pin to net - automatically create net on clicked target?
For this case, we are starting with a layout mostly done in L that has pcells but has no nets at all.In XL, when using Connectivity -> Nets -> Assign to assign an instance pin to a net, the...
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How to open Cadence 6.15 using AMS CMOS 0.35um design kit
Hello guys,I have used AMS CMOS 0.35um design kit 4years before, but I forgot how to open Cadence now. Does anyone know?For example, -csh-(what is here?)-virtuoso & (or ams?)Thanks in advance.Best...
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CDF parameters constantly revert back to prior settings
So I routinely create libraries where we release it as an IP, with only layout, symbol, spectre and auCdl views for the customer to access.The spectre and auCdl views have CDF parameters such as model,...
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Ambiguity Threshold in PVS-LVS
Hello all,I am working on a project where use a number of std filler cells. In LVS, these filler cells gave parameter missmatches, with the warning of ambiguous cells in the design.So I adjusted the...
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Controlling combinations in Techgen / Techgen for Quantus-FS only?
I'm trying to understand what options, if any, I might have for controlling what different combinations of layers, widths, and spacing are used in a "Techgen -simulation" run. This is EXT17.12. Also...
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Copy adexl view without history
Hello,I would like to have 2 adexl views and I would like to create a copy of the first adexl view without the History. The reason is that I want to simulate at the same time with two different...
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error in AMS simulation
Hello, I'm stuck with an error in my simulation that prevents me to see any results.I have a system with one digital block (Verilog) and several analog blocks. I'm using the extracted views (with...
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LEF generation from abstract is missing class,symmetry, origin information
HI ,I am trying to generate LEF file of an abstract (top level cell: TOP_CELL). Eventhough LEF is getting generated it is missing the following...
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Creating all pin symbol containing inherited power\ground connections
Hi,I am working on Virtuoso, version IC6.1.7-64b.500.4. I am using inherited connections in the schematic. AFter parasitic extraction, I observe that the inherited connections are missing in the...
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Distributed Processing Library command line
I've been looking in to how I can get multiple machines involved in a Techgen run. I read the DPL User Guide and it suggests some command line utilities for verifying the DPL config file...
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