Please help me with this issue, When I ran LVS in my design i see this message, I am tried to solve this issue.( Design FinFet 18nm design process).Please help me fixed this issue.
↧
Channel:
Cadence Custom IC Design Forum
X
Are you the publisher?
Claim or
contact us
about this channel.
X
0
Channel Details:
- Title: Cadence Custom IC Design Forum
- Channel Number: 3711455
- Language: English
- Registered On: July 11, 2012, 10:00 pm
- Number of Articles: 4906
- Latest Snapshot: May 14, 2025, 11:43 pm
- RSS URL: http://feeds.feedburner.com/cadence/community/forums/38
- Publisher: https://community.cadence.com/cadence_technology_forums/f/custom-ic-design
- Description:
- Catalog: //kittereen4.rssing.com/catalog.php?indx=3711455
© 2025 //www.rssing.com